Design Engr Resume Samples

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JW
J Welch
Jarrell
Welch
9927 Alicia Expressway
Phoenix
AZ
+1 (555) 912 5183
9927 Alicia Expressway
Phoenix
AZ
Phone
p +1 (555) 912 5183
Experience Experience
Boston, MA
Asic / Layout Design Engr
Boston, MA
Little-Smitham
Boston, MA
Asic / Layout Design Engr
  • Work with DDR PHY team, package engineers and system engineers to meet design specs
  • Work with global team
  • Provide subject matter expertise & technical leadership in design of High Speed IOs such as DDR
  • Perform scheduling duties, Remote site interaction etc
  • Knowledge of signal integrity issues (ie. clock/data routes, differential routing, shielding)
  • Exposure to scripting (ie. TCL, PERL, etc…)
  • Synopsys is looking for Senior Analog/Mixed-Signal Layout Engineer, who is responsible for design and development of analog and custom digital layouts for High speed IP’s
Phoenix, AZ
Analog Design Engr, Senior
Phoenix, AZ
Cole, Yundt and Bashirian
Phoenix, AZ
Analog Design Engr, Senior
  • Participate in establishing CAD and physical design methodologies for correct by construction designs
  • Provide subject matter expertise and technical leadership in design of high speed I/Os such as DDR
  • Identify and refine circuit architectures to achieve optimal power, area and performance targets
  • Review SerDes standards to develop analog sub-block specifications
  • Work with DDR PHY team, package engineers and system engineers to meet design specifications
  • Perform block level verification to close the design to meet timing, area and power constraints
  • Work with the layout team to come up with efficient layout design for the circuits including floorplan, pin placement and power grid etc
present
Chicago, IL
Comm System Design Engr Senior
Chicago, IL
MacGyver-Lindgren
present
Chicago, IL
Comm System Design Engr Senior
present
  • Supporting complex configurations, providing ongoing troubleshooting, and recovering outages
  • Generating system documentation including: Diagrams, Rack Elevations, Plate/Panel Details, Electrical load specification
  • Troubleshooting both LM and F-35 ALIS program equipment and supporting network equipment
  • Providing technical assistance to clients relating to operation, use, and maintenance of LM/GFE workstations and network equipment
  • Providing technical training and supervision to teammates and clients
  • Configuring and maintaining Call Managers, Voice Gateways, Routers, Switches, Firewalls, Session Border Controllers, Session Routers
  • Updating Standard Operating Instructions (SOI)
Education Education
Bachelor’s Degree in Electrical
Bachelor’s Degree in Electrical
University of Delaware
Bachelor’s Degree in Electrical
Skills Skills
  • Have Domain knowledge of low power Design techniques
  • Good analytical skills
  • Good Team player
  • Good communication skills
  • Self-motivated and Good analytical skills
  • Around 3 years hands-on experience in analog & mixed signal design/verification
  • Expertise with Cadence / Synopsys / Mentor / Redhawk tool set
  • Expertise in Floorplanning / Power Estimation and EMIR analysis / Physical verification and Padring implementation
  • B.Tech/BE or ME from reputed college in Electronics Engineering
  • Have design knowledge of Phase Locked Loops (PLL), Crystal Oscillators (XOSC), bias generators, reference circuits, Low Drop-Out regulators (LDO) and DC-DC converters, high speed/general IOs, Data converters etc
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15 Design Engr resume templates

1

Electronic Design Engr Resume Examples & Samples

  • BSE, BS in Electrical Engineering, MSEE is a plus
  • 5+ years experience in a design engineering role
  • High level of interest and a strong understanding of system level design / integration, experience in power electronics product design is a plus
  • Knowledge of and experience in designing products to UL/CSA/CE standards is a plus
  • Working knowledge of NPI Phase Gate and ECRO Change Management processes
  • Experience with Mentor Graphics Expedition or other industry standard E cad software
  • High level of analytical troubleshooting and problem solving ability where problems are unusual and difficult
  • Proficient in the use of Mathlab or equivalent
  • DFSS Certification and PMP is a plus
2

Comm System Design Engr Senior / Hill AFB Resume Examples & Samples

  • Assisting Extranet Team Lead with determining associated IT needs
  • Coordinating F-35 Extranet equipment installations with LM and the local Communications facilities
  • Coordinate with LM MST on functions for this location to include technician training, customer training programs, inventory and administrative information tracking, maintenance tracking, and vendor management – affiliated with the F-35 ALS Extranet
  • 4) Must hold an active DoD Secret clearance and be able to obtain and hold Special Access Program (SAP) clearances
  • Experience in Layer 2 and 3 Networking
  • Experience in both Windows and Unix/Linux systems administration and operating systems
  • Experience with network routers, switches, taps and firewalls
  • Demonstrated experience with the management, design, and installation of servers, routers, switches, and network taps in a business environment
  • Extensive troubleshooting experience with network hardware including but not limited to Juniper/Cisco switches, routers and Net Optics taps
  • 2) Proficiency in all MS Office applications
  • 3) Familiarity with existing LM products and processes, to include Joint Strike Fighter (JSF) F-35 hardware and software
  • 5) Demonstrated network administration skills, to include
  • Expertise developing and maintain training materials
3

Comm System Design Engr Senior Resume Examples & Samples

  • Serving as Network Site Support Administrator on the F-35 ALIS Extranet team
  • Provide technical training and supervision to teammates and clients
  • Ability to build and work with Network modeling tools
  • Systems administration experience with servers and network installations/integrations
4

Asic / Layout Design Engr Resume Examples & Samples

  • Experience in Analog Mixed-signal layout and verification of high-speed digital and/or DDR IOs, Critical signal inclusion
  • Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies
  • Solid understanding of CMOS and FinFET layouts and process technology in 28nm and smaller
  • Good understanding of basic ESD and latchup layout design considerations
  • Familiarity with ASIC physical design flow: LEF generation, Place & Route & understanding of top level verification flow, DRC/LVS, LPE
  • Remote site interaction, layout co-ordination activities, ability to foster accountability and ownership through hands-on technical leadership
  • Provide subject matter expertise & technical leadership in design of High Speed IOs such as DDR
  • Perform scheduling duties, Remote site interaction etc
  • Work with local team to support critical layout and floorplanning requirements
  • Coordination duties with other layout teams both in Bangalore and globally, to detail out layout activities and obtain layout deliverables. This includes reviewing and quality checking from remote Layout teams
  • Strict flow adherence and policing of internal policies to secure schedules
5

Asic / Layout Design Engr Resume Examples & Samples

  • Experience in Standard Cell layout and verification
  • Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, advanced floorplanning techniques, understand digital flow
  • Good understanding of CMOS layouts and process technology in 28nm and smaller
  • Good understanding of ASIC physical design flow: LEF generation, Place & Route
  • Good understanding standard cell abutment rules and requirements, EM and IR considerations, DFM, etc
  • Scripting skills for layout automation is advantage
  • Standard Cell Layout design including verification and validation
  • Work with global team
6

Asic Physical Design Engr Resume Examples & Samples

  • Ability to understand Verilog HDL code for commonly used logic functions and be able to use synthesis
  • A strong desire to learn, explore & implement at new technologies. Demonstrates good analysis & problem-solving skills. Resolves issues in creative ways
  • Hands-on knowledge on scripting using tcl, perl is a must
7

Asic / Layout Design Engr Resume Examples & Samples

  • Memory compiler block placement, power rings and interconnects routing in memory macro
  • Apply basic to moderate problem solving skills. Able to do project status reporting
  • Layout Design tools (preferably CD) and Schematic capture, DRC LVS Verification Tools (preferably ICV, Hercules), Power analysis Tools (preferably HSIM PWRA/XARA)
  • Scripting languages (preferably TCL, C-shell, Perl)
  • Taking initiative, Adaptability and flexibility as per business requirements
  • Be a positive participant, cultivator, eager to learn, engage curiosity, take initiative and active team player
8

Analog Design Engr, Senior Resume Examples & Samples

  • Recent experience delivering High Speed I/O or DDR I/O designs for low power wireless devices
  • Solid understanding of related CMOS and FinFET process technology and associated issues in 28nm and smaller
  • Familiarity with ASIC flow: Synopsys libraries, LEF generation, Place & Route & understanding of top level verification flow
  • DDR2/DDR3/DDR4 design experience including LPDDR/LPDDR2/LPDDR3/LPDDR4
  • Additional preferred experience in design and development of GPIO's, Special high speed IO's such as LVDS, USB, MIPI, DigRf, PLL's, ADC, etc
  • 3+ years CMOS/FinFET IO and Mixed Signal circuit development expertise
  • DDR / LPDDR High Speed I/O Circuit design including GPIO and Special IO’s
9

Analog Design Engr Resume Examples & Samples

  • Recent experience delivering High speed IO design including Latest DDR I/O designs for low power wireless devices
  • I/O design methodology & flow, Calibration, JTAG design requirements, understanding of analog circuitry, good understanding of ESD and LU based design concepts. Good understanding on the reliability aspects of designs such as Ageing and MC simulations
  • Familiarity with: JEDEC requirements for DDR interfaces & standards; Power & Signal Integrity
  • Ability to foster accountability and ownership through hands-on technical leadership
  • 10+ year's CMOS/FinFET IO and Mixed Signal circuit development expertise
  • DDR / LPDDR I/O Circuit and layout design including GPIO and Special IO’s
  • Provide subject matter expertise and technical leadership in design of high speed I/Os such as DDR
  • Work with DDR PHY team, package engineers and system engineers to meet design specifications
10

Asic / Layout Design Engr, Senior Resume Examples & Samples

  • Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc
  • Scripting skills for layout automation is a plus
  • Excellent written and verbal communication skills in interactions with customers, and internal development teams
  • High Speed DDR/LPDDR I/O Layout design including GPIO and Special IO’s
  • Work with DDR PHY team, package engineers and system engineers to meet design specs
11

Asic / Layout Design Engr, Senior Resume Examples & Samples

  • Strong knowledge of physical verification: DRC, LVS, ANT, ERC, EM-IR, DFM, Extractions etc
  • Deep understanding of various embedded memory architecture: Low power, high density, low standby power, High speed, Synchronous asynchronous architecture and various combination of such figure of merits
  • Strong understanding of memory layout techniques: dense designs, regular style, DFM compliant layout, matching (local and global), shielding, etc
  • Life time effect know how (EM, IR drop, Self-heating, HC, NBTI, PBTI, etc.)
  • Timely response to customer query technically within the set time limits
  • Excellent communication skills, Good Analytical skills/problem solving
  • Team player, Eager to learn, engage curiosity, develop deep competency, challenge each other and take initiative
12

Asic Physical Design Engr Resume Examples & Samples

  • Knowledge of backend IC design flows
  • Capability to work as a team member and promote excellent working relationships
  • Knowledge of Verilog/VHDL would be advantageous
13

Asic Physical Design Engr, Senior Resume Examples & Samples

  • Has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints
  • Has proven experience contributing to project tape-outs
  • Can contribute to enhancing the best practices of the physical design flow
  • Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements
14

Analog Design Engr Resume Examples & Samples

  • Recent experience delivering Latest GPIO or DDR I/O designs for low power wireless devices
  • I/O design methodology & flow, Calibration, understanding of analog circuitry, good understanding of ESD and LU based design concepts. Good understanding on the reliability aspects of designs such as Ageing and MC simulations
  • 5+ year's CMOS/FinFET IO and Mixed Signal circuit development expertise
15

Asic Physical Design Engr Resume Examples & Samples

  • Has solid engineering understanding of the underlying concepts of IC design
  • Is an expert with the implementation flows and methodologies for deep sub-micron designs
  • Has experience in high performance digital design and CAD, high-speed design, low-power design, high speed clock design and distribution
  • Has experience in timing closure, signal integrity
  • Has good software and scripting skills (Perl, Tcl, Python, .); knowledge of CAD automation methods
16

Asic / Layout Design Engr Resume Examples & Samples

  • Knowledge of CMOS processes and issues in deep submicron process technologies
  • CMOS circuit design and layout design concept, basic understanding of Standard cell layout, familiarity with basic finfet, multi pattern, logic library will be an advantage
  • Familiarity with ASIC design flow
  • Good written and verbal communication skills in interactions with internal development teams
17

Asic / Layout Design Engr Resume Examples & Samples

  • Diploma in EE with 4+ years of relevant experience,
  • BE in EE with 3+ years of relevant experience,
  • Required skills
18

Analog Design Engr, Senior Resume Examples & Samples

  • Generate block/chip level spec for the circuits
  • Work with the layout team to come up with efficient layout design for the circuits including floorplan, pin placement and power grid etc
  • Develop and validate high performance Circuit requirements using SPICE
  • Perform block level verification to close the design to meet timing, area and power constraints
  • Implement ECOs to fix timing, noise and EM IR violations when necessary
  • Participate in establishing CAD and physical design methodologies for correct by construction designs
  • The ideal candidate will have 6+ years of Circuit Design experience on Digital or Analog mixed Signal
  • Knowledge about industry standards and practices in SPICE
  • Experience in developing and implementing Circuit specifications
  • Solid Understanding of all aspects of Circuit Design
  • Working knowledge of Extraction and STA methodology and tools
  • Good understanding of Circuit Verification tools like EMIR, Noise, SigEM, clocks etc
19

Analog Design Engr Resume Examples & Samples

  • Design innovative analog and mixed-signal integrated circuits
  • Developing circuit specifications working from published SerDes protocols and standards
  • Select/create circuit architectures based on practical experience and knowledge of current circuit literature
  • Analyze and explain circuit behavior and limitations
  • Implement rigorous simulation test-benches to verify circuit performance
  • Incorporate test and tuning controls
  • Participate in critical peer reviews
  • Clearly document all circuit details
  • Guide, implement and review IC layouts
  • Work with a cross functional design team of analog and digital designers from a wide variety of backgrounds
  • Master’s in EE and related fields
  • Experience in designing at least two of the following key functions: Clock and Data Recovery, PLLs, Transmitters, Receivers, Bandgaps, ADC/DAC, DC-DC/LDO
  • Experience with tools for schematic entry, IC layout and SPICE simulation
  • Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture
  • Experience with TCL, perl, C, python, MATLAB, or other scripting languages
  • Good verbal English skills
20

Analog Design Engr, Senior Resume Examples & Samples

  • Schematic design,
  • Running simulations in hspice/finesim/xa,
  • Direct/coordinate with layout designers to generate layout that address advanced technology constraints,
  • Present ideas/results from investigations and analysis to peers,
  • Direct and address design issues with respect to back-end and electrical checks, and
  • Drive design to tape-out quality
21

Comm System Design Engr Senior Resume Examples & Samples

  • Coordinate with LM on functions for this location to include technician training, customer training programs, inventory and administrative information tracking, maintenance tracking, and vendor management – affiliated with the F-35 ALS Extranet
  • 7) Able to withstand extreme weather conditions in varying climates
  • 8) Able to lift and carry 100+ pounds for 25 or more yards
  • 9) Travel outside the local region is anticipated and will include OCONUS and CONUS bases and other locations (ship or shore) in support of requirements
  • 10) Time zone differences may require adjusted shift schedule as necessary to participate in telcons or VTCs with external agencies
  • 11) Deployment and continued employment is contingent upon successful completion of the OJT required at Lockheed Martin’s training locations prior to international assignment. These locations may include but are not limited to: Luke AFB, AZ; Nellis AFB, NV, Hill AFB, UT; Eglin AFB, FL; Edwards AFB, CA; Fort Worth, TX; Orlando, FL; Yuma, AZ; Beaufort, SC
  • 12) Successful candidate must be capable of passing medical, dental and overseas screening requirements and must maintain their medical fitness for this position as a condition of employment
22

Comm System Design Engr Senior Resume Examples & Samples

  • 9) Travel outside the local region is anticipated and will include USMC/USAF/USN/USA bases CONUS and other locations (ship or shore) in support of requirements. For the purposes of this effort, the T-AVB and MEU ships, wherever they may be located, are included in the definition of "USMC Bases." Guam, Australia, Singapore, Thailand, Alaska, PI, Korea, Wake Island, Hawaii, Malaysia, or any other in the Pacific AOR or deemed necessary
  • 10) Must meet all medical, dental and overseas screening requirements as directed by the local commander if ordered to deploy, to include completing forms DD2807, Medical Rider form, Navmed 1300-1, NavPers 1300-16. (Iwakuni is more restrictive than Okinawa or other OCONUS bases)
  • 11) Time zone differences may require adjusted shift schedule as necessary to participate in telcons or VTCs with external agencies
  • 12) Deployment and continued employment is contingent upon successful completion of the OJT required at Lockheed Martin’s training locations prior to international assignment. These locations may include but are not limited to: Luke AFB, AZ; Nellis AFB, NV, Hill AFB, UT; Eglin AFB, FL; Edwards AFB, CA; Fort Worth, TX; Orlando, FL; Yuma, AZ; Beaufort, SC
  • 13) Successful candidate must be capable of passing USMC medical, dental and overseas screening requirements and must maintain their medical fitness for this position as a condition of employment
23

Comm System Design Engr Senior Resume Examples & Samples

  • Serving as communications systems engineer for Lockheed Martin telecommunications systems (PBX) including both TDM and VoIP technologies
  • Service Management to include Incident, Change and Service Request Management
  • Performing Adds, Moves, and Changes on the Enterprise Voice Network
  • Responding, replacing, and repairing voice and data communication equipment to maintain optimum availability for the customer base
  • Problem coordination and escalation with LMC Enterprise Voice Program and various hardware vendors
24

Analog Design Engr, Senior Resume Examples & Samples

  • Knowledge of Linux and Windows operating system at user level
  • Familiarity with one or more IC design CAD packages required
  • Organizational skills essential
  • Good Knowledge and 5+ years of experience in analog schematic design
  • Familiarity with layout design
  • Independently resolves a wide range of issues in creative ways on a regular basis
  • Customarily exercises independent judgment in selecting methods and techniques to obtain solutions
  • Performs in project leadership role and contributes to complex aspects of a project
  • Determines and develops approach to solutions
  • Work is independent and collaborative in nature
  • Provides regular updates to manager on project status
  • Represents the organization on business unit and/or company-wide projects
  • Guides more junior peers with aspects of their job
  • Frequently networks with senior internal and external personnel in own area of expertise
25

Comm System Design Engr Stf Resume Examples & Samples

  • Working knowledge of call center network system components and understanding of how voice and network interface
  • A critical thinker who can plan, develop, and implement companywide telecommunications infrastructure
  • Toll Free number network implementation
  • Knowledge of call detail and call volume analysis
  • Advanced functional knowledge of a Call Center networks, call flows and call routing
  • Network monitoring, support and administration experience required. Knowledge of telecommunications infrastructure a plus. Telecom / Broadband (DSL / T1, Cable, 3G, etc.) and project management experience highly desirable
  • Knowledge of local and long distance carrier knowledge, computer/telephony integration (VoIP), disaster recovery development
  • Must have working knowledge of Microsoft Outlook, Access, Excel, Project, PowerPoint and Visio
  • Advanced analytical, critical thinking and problem solving skills
  • Knowledge of Customer Service Center processes, policies and procedures
  • Has a firm understanding of hosted voice services with SIP trunk services and be able to provide explanation and guidance on a system implementation and configuration
  • Relevant functional/business analysis experience in support of a telecom client or projects, along with a strong understanding of the Agile methodology
  • Requires basic skills in teamwork, communication, presentation, and time management to work effectively with teams throughout the organization
26

Design Engr Lead-emulation / Verification Resume Examples & Samples

  • Evaluate and deploy the evolving verification methodologies to handle increasingly complex SoC/IP designs within aggressive, market-driven schedules
  • Ability to work well as part of a team both locally, and also with remote or multi-site teams
  • Driven and competitive when dealing with the outside, collaborative when dealing with the inside
  • Self starter with 6-8 years of experience on SOC/Chip level/Cluster/IP verification on multimillion Gate and complex Design with multiple clocks and power domains with minimal supervision
  • Testbench and Testplan development to address Analog/Mixed signal and Testability aspects of the chip along with functional requirements
  • Experience and working knowledge of HVLs (SV/C++/SC/e/VERA), HDLs (Verilog/VHDL),PLI/DPI, simulators (IUS/Questa/VCS) is a MUST
  • Experience in automotive protocols like LIN, CAN, Flex, Graphics/Multimedia/Networking protocols like PCIe, MIPI, H.264, Ethernet, USB, ITU T.656 would be an advantage
  • Exposure to formal verification methodology, assertions/SVA, functional coverage, gate level simulations, verification planner and regression management
  • Experience in Low power verification using CPF/UPF
  • Exposure to pre silicon validation/emulation (Palladium, Zebu) would be a big advantage
27

Asic / Layout Design Engr, Senior Resume Examples & Samples

  • Experience in leading design activities technically to create differentiating memory IPs
  • Experience in providing architectural solutions, to achieve required performance (area, power and delay), provide mature estimation and drive various such activities to their completion by delivering SRAM/ROM in time and as per commitment and expected quality
  • Ability to understand the existing off the shelf memory solution and propose innovative solution to enhance them to create differentiate memory IP as per dynamic business requirements
  • Provide technical consultancy to XYZ customers on existing off the shelf memory offerings and on future possible solutions
  • Create memory IP solution roadmap to cater to the future demand
  • To be involved in customer discussions to understand their requirements and translate them into memory IP requirements
28

Asic / Layout Design Engr Resume Examples & Samples

  • Experience in Embedded memory layout design and verification
  • Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, advanced floor planning techniques, understand digital flow
  • Good understanding of CMOS layouts and process technology in 16nm and smaller
  • Good understanding of EM and IR consideration, tools and flows, debugging and fixes
  • Memory Layout design and compiler release including verification and validation
29

Asic / Layout Design Engr Resume Examples & Samples

  • Experience required: 3- 5 Years
  • Fundamentals of CMOS, Fabrication Methodology
  • Good understanding of embedded memory architecture
  • Expertise in physical design methodologies/ Physical design phases: Memory compiler blocks Floor planning, Place and route, physical verification DRC/LVS, Signal integrity
  • Tools: Sign-off quality tools in each design phase. Layout Design tools (preferably CD), DRC LVS Verification Tools (preferably ICV), IRDROP and EM analysis Tools (preferably XARA PWRA)
  • Knowledge of design principles and practices
  • Scripting languages knowhow (preferably SHELL TCL, Perl)
  • Have working knowledge advanced design tools. Produce technical design documents and maintain accurate and thorough documentation of work. Be a positive participant, cultivator and active team member
  • Has a strong desire to learn and explore new cutting edge technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience of CAD tool development are required. Applies company policies and procedures to resolve routine issues. Follows standard practices and specific, outlined, and detailed procedures in analyzing situations or data from which answers can be readily obtained. Builds routine working relationships internally. Contacts are primarily with direct manager and other peers in the group or department
30

Software Design Engr Resume Examples & Samples

  • Having complete knowledge and experience in the field, is able to handle seldom and unusual occurring job events
  • Ability to complete complex and difficult assignments
  • May determine methods and procedures on new assignments and provide guidance to nonexempt personnel
  • Knowledge of assigned product(s), company functions, service policies and procedures and good communication skills
  • Proficiency in computer applications, languages, technologies, advanced set-up and configurations, troubleshooting, and system design, and/or capabilities required for the position
  • Bachelor's degree in related field and 10+ years related experience
  • Advanced degree in related technical field desired
31

St, Fpga Design Engr Resume Examples & Samples

  • 8+ years of FPGA design
  • Hands on experience with packet domain
  • Expertise in Verilog Hardware Description Language
  • Working knowledge of FPGA development cycle (Coding, synthesis, implementation, timing closure, image generation)
  • Individual ownership of standalone FPGA designs
  • Support for HW board bring-up
  • Working knowledge of lab equipment such as oscilloscopes and logic analyzers
  • Knowledge of scripting languages
  • Working knowledge of Ethernet (1G/10G/40G/100G)
  • Working knowledge of packet domain (packet switching, packet processing etc)
  • Experience designing FPGAs with embedded soft or hard processors
  • FPGA implementation of closed loop control systems
32

Comm System Design Engr Senior Resume Examples & Samples

  • Serving as communications systems engineer for the Space Systems Cisco Unified Communications Manager administering and troubleshooting various telecommunications systems (PBX) including both TDM and VoIP technologies
  • Performing Adds, Moves, and Changes
  • Problem coordination and escalation with LM Enterprise Voice Infrastructure and various hardware vendors
33

Comm System Design Engr Senior / Eglin Resume Examples & Samples

  • Troubleshooting both LM and F-35 ALIS program equipment and supporting network equipment
  • Field testing of LM and F-35 ALIS program network equipment
  • Project Management to support F-35 ALIS network expansion and migration
  • Provide technical assistance to clients relating to operation, use, and maintenance of LM/GFE workstations and network equipment
  • Work with customers and internal personnel to manage related IT projects and provide customer service and technical support
  • 3) Self Starter & the ability to multitask
  • 5) Must be willing to work off hours, to include 0300-1200, 0700-1600, 1000-1900, and/or 1500-2400 depending on operational needs
  • Demonstrated ability to analyze and prepare designs for networks in relation to intrusion detection systems
  • Working knowledge of reading blueprints and wiring server racks
  • 1) Excellent verbal and written communication skills and the ability to create presentation material for Base Leadership (e.g. Officers and management)
  • Ability to provide high-level network, systems administration and technology management
  • Utilizing vendor relationships to support Extranet expansion and technology refresh
  • Administration, troubleshooting and maintenance for network systems
  • 6) COTS/developed software skills
34

Analog Design Engr, Senior Resume Examples & Samples

  • Review SerDes standards to develop analog sub-block specifications
  • Identify and refine circuit architectures to achieve optimal power, area and performance targets
  • Propose design and verification strategies that efficiently use simulator features to ensure highest quality design
  • Oversee physical layout to minimize the effect of parasitics, device stress, and process variation
  • Present simulation data for peer and customer review
  • Document design features and test plans
  • Consult on the electrical characterization of your circuit within the SerDes IP product
35

Asic Physical Design Engr, Senior Resume Examples & Samples

  • Has good communication skills, ability to think and communicate at different levels of abstraction
  • Has demonstrated experience as a technical contributor on physical design projects and as project lead
  • Autonomous, timely decision maker and ability to cope with interrupts are required
  • Has intimate knowledge of the full design cycle from RTL to GDSII
  • Is an expert with the physical implementation flows and methodologies in deep sub-micron designs
  • Has experience in timing closure including margining/variation; and signal integrity
  • Can develop and refine timing constraints through the demonstrated ability to work with front end designers
  • Has worked at the chip level and understands the requirements for wire bond or flip chip packages
36

A&MS Layout Design Engr, Senior Resume Examples & Samples

  • SRAM memory layout design
  • Basic CMOS circuit/device fundamentals
  • Experience in memory/logic design and verification
  • Ability to research and study technical documentation
  • Ability to quickly study and apply new tools and methodologies
  • Knowledge of Linux/UNIX environment
37

Lead Design Engr-dft Resume Examples & Samples

  • Bachelor's Degree in Electrical/Electronic Engineering
  • 8-12 year(s) of working experience in DFT
  • Must possess a strong knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation
  • Standard DFT techniques: Memory BIST and Repair/ Scan/ On-Chip Compression/ At-speed Scan/Boundary Scan/Logic BIST in one or more complex SOCs
  • Strong Knowledge/Understanding of Synthesis & STA
  • Experience with silicon-bringup is a plus
38

Design Engr Resume Examples & Samples

  • SOC Hierarchical Planning for multimillion gate design
  • Interaction with Systems team on Package / Padring implementation / Closure
  • Floorplan and Power Grid Closure (EM/IR closure)
  • Power Estimation and low power Design
  • Physical Verification signoff
  • ESD/EMC Signoff
  • Support to FA analysis team for debugs
  • B.Tech/BE or ME from reputed college in Electronics Engineering
  • More than 5 years of hands-on experience in Backend design of multi-million gate SOC
  • Expertise in Floorplanning / Power Estimation and EMIR analysis / Physical verification and Padring implementation
  • Expertise with Cadence / Synopsys / Mentor / Redhawk tool set
  • Have Domain knowledge of low power Design techniques
  • Self-motivated and Good analytical skills
  • Good Team player
39

Senior MTS Elect Design Engr Resume Examples & Samples

  • 10 or more years in the wireless space with the majority of that time spent on Bluetooth IP development
  • Strong understanding of Bluetooth building block IP in particular the Bluetooth MAC
  • Strong understanding of the Bluetooth standard up to and including 5.1
  • Lead designer or architect for at least one mass produced SoC with integrated BT core
  • HDL coding skills. Can be Verilog, VHDL, HLS, or other
  • Understanding of scripting and Makefiles
  • General knowledge of DV, synthesis, FGPA, and/or general ASIC flows is a plus
  • General understanding of working within a Linux environment
  • Basic lab skills. Be in a position to work autonomously on the bring-up bench
  • MSEE preferred. Strong candidates meeting all the other criteria though will be considered
40

Design Engr Resume Examples & Samples

  • Act as Analog & mixed signal analysis & verification engineer at SOC level for assigned project/modules
  • Analysis of analog & mixed signal architecture & integration of analog IPs for assigned SOC/module
  • Interpret analog/supply specifications of the SOC to achieve quality targets
  • Analysis & verification of test-modes & DFT strategy for analog IPs
  • Support lab debugs for post silicon issues
  • Support test development engineers for production ramp up/debugs
  • Support / Mentorship of junior team members
  • Participate regular peer to peer reviews and design reviews
  • Support technical queries from systems/application engineers
  • Around 3 years hands-on experience in analog & mixed signal design/verification
  • Have design knowledge of Phase Locked Loops (PLL), Crystal Oscillators (XOSC), bias generators, reference circuits, Low Drop-Out regulators (LDO) and DC-DC converters, high speed/general IOs, Data converters etc
  • Have exposure in ultra low power design techniques (multi supply domain, power gating, clock gating)
  • Have know how in interfaces to other domains (supply/power domain crossing) such as level shifter, isolation, analog test-bus etc
  • Have SOC level analog & mixed signal integration and verification expertise
  • Have experience in co-simulations techniques with leading EDA vendors
  • Have a creative attitude
41

Design Engr Iv-experienced DFT Engineer Resume Examples & Samples

  • 4-8 year(s) of working experience in DFT
  • Must have a firm understanding and hands-on experience on industry
  • Knowledge/Understanding of Synthesis & STA
  • Creative problem-solving skills and the ability to logically break complex problems down to manageable components
  • Good written and verbal communication skill
  • Applicants must be willing to work in Noida
42

Asic Physical Design Engr, Senior Resume Examples & Samples

  • Has engineering understanding of the underlying concepts of IC design
  • Has knowledge of the full design cycle from RTL to GDSII
  • Is eager to become an expert with the physical implementation flows and methodologies in deep sub-micron designs
  • Has academic and practical exposure in high performance digital design and CAD, high-speed design, low-power design, high speed clock design and distribution, timing closure, signal integrity
  • Has good scripting skills; knowledge of CAD automation methods
  • The candidate must have English speaking level allowing interaction with the larger product team to understand design constraints, deliverable formats, and customer requirements
  • The candidate must be able to follow and improve defined design methodologies and processes to implement and deliver on schedule
43

Senior Elect Design Engr Resume Examples & Samples

  • Debug tests to deliver functional correct blocks
  • Experience in the verification of design such as DDR3, DDR4 , NAND SLC,MLC mode
  • Strong knowledge C
  • Experience with scripting language(Python, Perl, TCL , Shell)
  • Familiar with FPGA flow is preferred
44

Prin Elect Design Engr Resume Examples & Samples

  • BSc in Electrical Engineering, from a well-known university. MSc - Advantage
  • 5 - 12 years of experience in full chip and block level logic verification
  • Experienced and knowledgeable in advanced coverage based verification process using System Verilog and UVM
45

Senior Asic Design Engr Resume Examples & Samples

  • Develop verification definitions for various products
  • Take part in overall chip level coverage based verification work
  • Act as a reviewer for other team members work
  • Write proper documentation for work being done
  • BSc in Electrical Engineering, from a well-known university
  • 2 - 5 years of experience in full chip and block level logic verification
  • Experienced and knowledgeable in advanced coverage based verification process using System Verilog and UVM – Advantage
46

Elect Design Engr Resume Examples & Samples

  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Disciplined issue reporting, bug tracking and communication of design risks & status
  • Experience with EDA tools such as NCSIM, VCS, Modelsim, DC, PT
  • Strong communicator and team player
47

Elect Design Engr Resume Examples & Samples

  • Concept and architecture definition
  • Specification and documentation
  • Virtual prototyping (C++, SystemC, TLM)
  • RTL design (Verilog)
  • Verification (formal, SystemVerilog, UVM)
  • Hardware prototyping with FPGA platforms
  • Background in video and graphics processing
  • UVM based verification expertise
  • High-level synthesis know-how (behavioral synthesis)
48

Analog Design Engr, Senior Resume Examples & Samples

  • CMOS circuit design and layout methodology & flow; basic understanding digital circuits
  • Knowledge of SRAM memories is must
  • Memory compiler development knowledge is must
  • Spice simulation and layout drawing tools knowledge is required
  • Ability to execute assigned circuit design tasks with best product quality and efficiency
  • ​Minimum of 3+ year memory circuit design experience
49

Prin Asic Design Engr Resume Examples & Samples

  • Knowledge of digital communication systems and low power, high speed digital data path design is a plus
  • Familiarity with MAC implementation/verification of communication systems/protocols such as 802.11, LTE etc is a plus
  • Be proficient in Verilog/VHDL, be familiar with C/C++
  • ARM based SOC verification experience
  • Familiarity with AMBA - AXI,AHB,APB protocols is a plus
  • Strong verification skills like test planning, debug
  • At least one script language (TCL, Perl, Python and etc)
  • Proficiency in SystemVerilog, SystemC, UVM, and/or VMM
  • “Assertion based verification” knowledge
  • Familiarity with UPF/CPF based Verification flow and GLS
  • Good problem solving, communication and documentation skills
  • 10-15yrs
50

Comm System Design Engr Senior Resume Examples & Samples

  • Project Management supporting F-35 ALIS network expansion and migration
  • Providing technical training and supervision to teammates and clients
  • Providing technical assistance to clients relating to operation, use, and maintenance of LM/GFE workstations and network equipment
  • Working with customers and internal personnel to manage related IT projects and provide customer service and technical support
  • Coordinating with LM MST on functions for this location to include technician training, customer training programs, inventory and administrative information tracking, maintenance tracking, and vendor management – affiliated with the F-35 ALS Extranet
  • 1) Strong systems & software engineering and/or system administration process background
  • 2) Good Communication & Verbal skills
  • 4) Prior Network administrator experience
  • Extensive troubleshooting experience with Unix, Linux, Solaris, Windows operating systems
  • 5) Must be a US Citizen or legally authorized to work in US as a permanent resident
  • 6) Must be capable of attaining a Secret Special Access Required clearance
  • 1) Excellent verbal and written communication skills and the ability to create presentation material
51

Elect Design Engr Resume Examples & Samples

  • Identify areas of testbench development suitable for automation
  • Define & develop the automation script (Perl, Python, Ruby)
  • Assist in the rollout of this automation across sites from Tokyo to Seattle
  • Manage the scripts during adoption
  • An excellent Bachelor’s degree or equivalent in Engineering or Computer Science
  • An understanding of digital design and verification
  • Design languages: Verilog, SystemVerilog, UVM/OVM/VMM
  • Scripting languages: Perl, Python, Ruby
52

Elect Design Engr Resume Examples & Samples

  • IC package Layout Design (WLCSP) experience is an added advantage *
  • Excellent written and verbal communication skills in the English Language
  • Proficient in AutoCad
  • Proficient in Geometric Dimensioning and Tolerancing
  • Knowledge of IC package assembly and manufacturing processes
  • Signal Integrity knowledge and experience is an added advantage
  • Training will be provided since this is an entry level position
53

Prin Elect Design Engr Resume Examples & Samples

  • B.E./B.Tech. with 12-13 years of experience or M.E./MTech. with 10-11 years of experience and specialization in VLSI design
  • Hands-on experience in DFT logic insertion, simulations and timing closure of large blocks/top
  • Experience as DFT lead for chips with large size
  • Expert user of Mentor/Logic vision DFT tools
  • Expert in Silicon bring up and failure analysis
  • Good at DFT low power architecture
  • Expert in scripting languages (shell, perl, tcl) and Make flow
  • ATE hands on experience will be a plus
  • Should be self-motivated and take initiatives to drive new methodologies
  • Should have strong written and verbal communication skills
54

Human Fctrs Design Engr Senior Resume Examples & Samples

  • Bachelors degree in Industrial Engineering, Human Factors Psychology, Mechanical Engineering, or closely related field
  • Human Factors Engineering practitioner who has experience with designing and conducting usability tests and task analyses
  • Effective, proven communications and presentations skills
  • Demonstrated pro-activeness and problem solving skills
  • Master’s degree in Industrial Engineering, Human Factors Psychology, or closely related field
  • Familiarity with human space flight
  • Previous interface with NASA customer
  • Lean 6 Sigma practitioner
55

Elect Design Engr Resume Examples & Samples

  • Good knowledge of digital simulators (Verilog)
  • Basic working knowledge of spice simulators
  • Operating Systems: Linux, Unix and Windows
  • Knowledge of RTL coding and synthesis is a plus
  • Excellent communication skills and ability to work in cross-functional teams
  • Knowledge of memory design/architecture is a plus
  • Experience with scripting/programming languages (PERL, Python, Ruby etc) is a plus
56

Comm System Design Engr Stf Resume Examples & Samples

  • Ability to obtain and maintain a DoD Secret Security clearance
  • 7+ years of proven senior level Network Engineering and LAN/WAN Communications experience in dynamic and demanding IT environments. Confirmed by related work experience
  • Demonstrated advanced knowledge and experience in the design and implementation of switching and routing protocols
  • Extensive troubleshooting experience with network hardware and software fault isolation, root cause analysis, and implementing corrective actions
  • Extensive network performance analysis tool experience
  • Candidate must have expert level experience troubleshooting network connectivity and/or peer to peer application issues at all levels of the TCP/IP stack via packet capture and analysis
  • Ability to successfully prioritize and work multiple projects and tasks concurrently
  • Demonstrated accountability for tasks and deliverables
  • Proven ability to effectively communicate detailed concepts and translating them into appropriate technical specifications
  • Proven ability to operate independently and exercise appropriate technical judgment
  • Ability to travel to other sites as required
  • Knowledge and/or experience supporting the LM MFC unclassified network infrastructure
  • Experience with Brocade Network Switches and Brocade Network Advisor
  • Demonstrated experience with Opnet VNE Server and/or Riverbed Application Response performance platforms
  • Experience or familiarity with Data Center enterprise-wide IT processes and systems
  • Proficiency/Certifications in both network and security areas (CCNA, CCNP, CCIE, CISSP, Security +)
  • Experience with Brocade, Cisco, F5, and WAN optimization platforms
  • Experience in information security infrastructure, including firewalls and VPN architecture
  • Experience with the development of Standard Operating Instructions and Disaster Recovery Plans
  • Experience managing vendor relationships for break/fix, root cause analysis, escalations, and technology refresh
  • Systems integration skills. Demonstrated experience integrating infrastructure components such as, but not limited to, network, server, storage, and security systems
  • Familiarity and/or experience supporting Software Defined Networks (SDN)
  • Exhibits strong customer service skills. Ability to communicate at a high technical level and also at a summarization level to interface with program leadership and EBS DV2 leadership
57

Design Engr-fpga Architecture Resume Examples & Samples

  • Help architect new features and feature enhancements in interconnect, clocking, configuration, logic and all other aspects of our FPGA and SOC architectures
  • Circuit design on industry leading process nodes as required for architectural analysis, test chip design et al
  • Digital logic design (Verilog/VHDL) to capture architecture definition and managing benchmark designs
  • Implement challenging designs in FPGA tool flow in help achieve timing closure, or estimate possible performance on new architectures, given intimate knowledge of the FPGA architecture
  • CMOS circuit design and logic design
  • HDL languages (Verilog/VHDL)
58

A&MS Layout Design Engr Resume Examples & Samples

  • Knowledge of physical design methodologies/ Physical design phases/ Floor planning, Place and route, physical verification, Signal integrity
  • IR/EM analysis of memories including back annotation of layout parasitic, physical verification using DRC and LVS tools
  • Work with moderate supervision. Produce technical design documents and maintain accurate and thorough documentation of work
  • Have basic task tracking and self-management skills
59

Senior Elect Design Engr Resume Examples & Samples

  • 1+ years with Master's Degree or 3+ years with Bachelor Degree in EE/CE
  • Experience on custom IC design skills
  • Experience on Mixed-signal SoC product with MCU and the peripheral IPs
  • Knowledge with a wide range of analog IP such as Band-Gap, OPAMP, Switch Cap, OSC, ADC, and so on
  • Layout experience and Physical verification experience
  • Experience on Memory design is plus
  • LATCHUP and ESD knowledge is plus
  • Understand digital verilog design and analog veriloga module
  • Experience in analog and digital simulation tools, ELDO, NANOSIM, and MODELSIM tools experience is plus
  • Proficiency in Perl, Tcl, Shell, assembly and C languages
60

Senior Elect Design Engr Resume Examples & Samples

  • Work with design team and FPGA platform customers to define the FPGA bitfile requirements and limitations
  • Work with IP team to define the hardIP FPGA model
  • Provide the hardware requirements to the hardware engineer from FPGA engineer view
  • Work on porting the full chip RTL to FPGA RTL, Replace the hardIP of the full chip with FPGA resource
  • Design test bench to check if the FPGA RTL is functionality as expected
  • Execute the FPGA synthesis, P/R and timing clean, provide the bitfile to FPGA platform customers
  • Work with design team and Verification to debug and solve the issues feedback from FPGA platform customers
  • As a key role of FPGA team, contribute to improve the productivity of the team
  • Familiar with SOC prototyping
  • Familiar with RTL based design and verification, tools, flow. With practical experience
  • Familiar with FPGA development tools and Flow
  • NCG from Tier 1 university
61

Software Design Engr Resume Examples & Samples

  • Analyze functional/technical requirements and perform a fit/gap against the OOTB (Out Of The Box) version of Cúram in production
  • Participate in Joint Application Development (JAD) sessions for detailed system design and development
  • Implement the configurations and extensions to the product following the IBM mandated Cúram development standards
  • Implement and unit test external interfaces to the DCAS System using SOAP/XML web services
  • Model service layer APIs (using Rational Software Architect) as Batch processes for implementing notices and reporting requirements
  • Design and implement the District specific SNAP/TANF eligibility rules using CER (Cúram Express Rules)
  • Design and implement workflows for deferred processing
  • Provide technical Tier 3 support to the production system
  • Create/maintain technical documentation
  • Apply Cúram FixPacks and upgrades in production
  • Write Junit Tests for unit testing and code coverage
62

Senior Elect Design Engr Resume Examples & Samples

  • BSEE (MSEE or PhD a plus)
  • Strong performance in Math and Physics
  • Coursework to include Analog design (amplifier, oscillator, PLL, control techniques), Power Circuit Design, Programming (CPP, Perl), VLSI design and layout (practical Cadence/Mentor tool experience)
  • Experience in lab environment
  • Experience with micro-controller a plus
63

Senior Asic Design Engr Resume Examples & Samples

  • Understanding requirements & specifications
  • Testplan & testbench development
  • Verification (Formal, SystemVerilog, UVM)
  • 2+ years industry experience in verification
  • Bachelor/Masters/PhD Degree in Electronic/Computer Engineering
  • Development of verification environments and methodologies at block level
  • Extensive knowledge of SystemVerilog / Verilog / OVM / UVM / VMM
64

Asic Physical Design Engr Resume Examples & Samples

  • Bachelors or Masters degree in electronics or electrical engineering (BSEE or MSEE) or equivalent from reputed universities with around 1-2 years experience in ASIC design
  • Gate level and circuit level understanding of CMOS logic design
  • Strong Synthesis,STA skills & ability to analyze timing using Primetime, ETS
  • RTL coding,Function verification & simulation,Equivalence checking,DFT
  • Familiar with backend ASIC design flow
  • Experience using Synopsys design tools (DC,DCT,PT,Formality),Cadence tools(RC,NCsim,conformal),Magma tools (Talus RTL/Design)
  • Should be familiar with the Low power concepts & UPF/CPF format
  • Scripting in TCL and Perl
  • Good communication, interpersonal skills and team player
  • Flexible, creative, and able to perform high quality work
65

Comm System Design Engr Senior Shiprider Resume Examples & Samples

  • Serving as Network Site Support Administrator on the F-35 ALIS USS Essex team
  • Reviewing network schematics, diagrams, and other program documentation to assist with development and preparation of cost estimates
  • Coordinating F-35 Network equipment installations with LM and the local Communications facilities
  • Generating system documentation including: Diagrams, Rack Elevations, Plate/Panel Details, Electrical load specification
  • Coordinate with LM MST on functions for this location to include technician training, customer training programs, inventory and administrative information tracking, maintenance tracking, and vendor management – affiliated with the F-35 ALIS Network
  • Provide tiered troubleshooting within the scope of a Problem Management and Network Management System in support of Contractor Logistics Support and F-35 ALIS program personnel
  • 4) Must be willing to work off hours, to include 0300-1200, 0700-1600, 1000-1900, and/or 1500-2400 depending on operational needs
  • 5) Must be able to obtain and retain DoD IAT Level II certification
  • 6) Prior Network administrator experience
  • Extensive troubleshooting experience with Unix, Linux, Windows operating systems
  • Demonstrated PC and networking skills, including NetMeeting, conferencing servers
  • Development of Standard Operating Instruction and other training skills and training material development experience
  • Certifications in the following Environments: Unix, MS-, NT-, X-Windows, Linux, CCNA
  • Knowledge of spanning technology in switches
  • 7) Software Engineering background and experience
  • 8) Integration & Test experience
  • 9) Final Transferable Secret clearance with a completed investigation within the last 6 years
  • 10) Previous experience with USN Ships and Shipboard Networks preferred
66

Senior MTS Elect Design Engr Resume Examples & Samples

  • Expertise in RFIC CMOS designs is highly desirable
  • Ideal candidates will have at least 10 years of CMOS RF IC design experience in several of the following areas
  • PLLs & Frequency Synthesizers
  • Transceivers baseband blocks (filters, VGA, ADCs & DACs)
  • System-level specification, floorplanning, characterization, and productization experience is desired
67

Comm System Design Engr Senior Resume Examples & Samples

  • Serve as the ALIS Network Administrator point of contact during ORE daily activities and scheduled events
  • Coordinate with LM on functions for this location to include technician training, customer training programs, inventory and administrative information tracking, maintenance tracking, and vendor management
  • 3) Self starter & the ability to multitask
  • 7) Must be able to obtain and retain a current DoD IAT Level II certification
68

Comm System Design Engr Stf Resume Examples & Samples

  • Serving as a Network Administrator for the Enterprise Voice System
  • Fault Isolation Troubleshooting of Enterprise Voice Network and associated Peripheral Components
  • Provide Customer Service and Technical Support to Lockheed Martin Customers
  • Problem coordination and escalation with Enterprise Voice System Vendors
  • Coordinating network equipment and cable infrastructure installations
  • Updating Standard Operating Instructions (SOI)
  • Configuring and maintaining Call Managers, Voice Gateways, Routers, Switches, Firewalls, Session Border Controllers, Session Routers
  • Supporting complex configurations, providing ongoing troubleshooting, and recovering outages
  • Willingness to work on-call rotation providing 24X7 support
69

Comm System Design Engr Senior Resume Examples & Samples

  • Must be willing to travel, to include Ship deployments for extended periods depending on operational needs. Position may require the ability to perform in an arduous duty environment and subject to all applicable U.S. Government requirements. A detailed list of these requirements will be available at the time of interview and employment will be contingent on agreement and compliance with such requirements
  • Successful candidate must be capable of passing USN medical, dental and overseas screening requirements and must maintain their medical fitness for this position as a condition of employment
  • Deployment and continued employment is contingent upon successful completion of the OJT required at Lockheed Martin’s training locations prior to international assignment. These locations may include but are not limited to: Luke AFB, AZ; Nellis AFB, NV, Hill AFB, UT; Eglin AFB, FL; Edwards AFB, CA; Fort Worth, TX; Orlando, FL; Yuma, AZ; Beaufort, SC
  • The selected applicant selected may be required to work at deployed locations, work rotating shifts, and work in excess of 40 hours per week
  • Relocation: Relocation package is available for this exciting position
  • Candidate will work/OJT stateside for several months prior to relocating to Sasebo
  • Candidates must have a Final Transferable Secret security clearance, last Periodic Reinvestigation must be within the last six years. Candidates must be able to attain and maintain Special Access Program (SAP) access
  • 5) Must be willing to work off hours, to include 0300-1200, 0700 -1600, 1000-1900, and/or 1500-2400 depending on operational needs
  • Extensive troubleshooting experience with network hardware including but not limited to Juniper/Cisco switches, routers and
  • 13) Successful candidate must be capable of passing USN medical, dental and overseas screening requirements and must maintain their medical fitness for this position as a condition of employment
  • Certifications in the following Environments: Unix, MS-, NT-, XWindows, Linux, CCNA
70

Comm System Design Engr Senior Resume Examples & Samples

  • **This position is intended to travel to new sites and help establish a "Ready for Operations" condition per current LM guidance. Additionally, members of this team MAY need to stay for an extended period at the new site to provide training to new or non-US ALIS Administrators - expected to be 120 days or less in length. Depending on the site(s), travel may exceed 50% of any given year. Due to these requirements, previous ALIS experience is required.*****
  • Serving as Network Site Support Administrator on the F-35 ALIS LRIP Standup Team team
  • Assisting Extranet Team Lead with determining follow-on IT needs
  • Coordinating F-35 equipment installations with LM and the local customer Communications points of contact
  • 5) Self Starter & the ability to multitask
  • 6) Must hold an active DoD Secret clearance and be able to obtain and hold Special Access Program (SAP) clearances
  • 7) Must be willing to work off hours, to include 0300-1200, 0700-1600, 1000-1900, and/or 1500-2400 depending on operational needs
  • 8) Prior Network administrator experience
  • Certifications in the following Environments: Unix, MS-Windows 7/Server 2012-, X-Windows, Linux, CCNA
71

Elect Design Engr Resume Examples & Samples

  • BS in Electrical Engineering, MS in Electrical Engineering preferred
  • Demonstrated success in the Classroom
  • Familiarity with CMOS circuits and processes
  • Educational Focus in either Analog, Digital, or Mixed Signal Design
  • Knowledge of the different types of Memory Products
  • Experience with verification tools such as SPICE for circuit verification or Verilog for digital verification
72

Prin Elect Design Engr Resume Examples & Samples

  • Candidate is expected to have deep understanding of low power design techniques
  • Candidate will be responsible to achieve die area, performance, power goals for blocks/top
  • Hands-on experience in physical design and timing closure of large blocks/top
  • Expert user of industry standard tools for physical design and signoff
  • In-depth knowledge of 40nm/28nm technologies and associated physical design challenges
  • Experience in low power checks will be a plus
73

Senior Elect Design Engr Resume Examples & Samples

  • Engaged in full custom circuit design activity for new product development, design center improvement
  • Involved in design productivity initiatives
  • Getting trained in CD design and other CY mandatory trainings
  • Detailed knowledge and understanding of device physics, analog circuits and CMOS fundamentals
  • Working knowledge of digital circuits and RTL
  • Good problem solving and communication skills
  • Ability to work with cross functional teams with Strong oral and written communication skills
74

Prin Elect Design Engr Resume Examples & Samples

  • PhD or MS in Electrical Engineering (or equivalent) preferred
  • Ideal candidates will have at least 5 years of CMOS RF IC design experience in several of the following areas
  • RF blocks used in transmitters and receivers
  • Front-end (LNA, mixers, PA drivers, PAs)
75

A&MS Circuit Design Engr Resume Examples & Samples

  • Designing, developing, and evaluating analog and mixed signal integrated circuitry
  • Generating design specifications
  • Determining design approaches and parameters
  • Developing and exercising dedicated environments for validation and characterization of designs
  • May participate in physical design layout and review of physical design layout of analog and mixed signal circuits
  • Generating documentation for circuit development, verification, and usage
  • May participate in evaluation and troubleshooting of analog and mixed signal circuits
  • 2+ years of relevant experience and BS/MS in Electrical Engineering or Computer Science
  • Basic knowledge in transistor level Analog and Mixed Signal circuit design and layout
  • Design and development experience of op-amps, differential amplifiers, level-shifters, and high speed IO interfaces
  • Deep understanding of CMOS process technology
  • Understanding ESD and Latchup requirements and device reliability rules
  • Working knowledge of Synopsys design tools, simulators (Hspice, Finesim, Waveview, ICV, Custom Compiler, Custom_Sim)
  • User level knowledge of Linux and Windows operating systems
  • Working knowledge of Verilog is a plus
  • Knowledge in TCL or Perl scripting language is a plus
  • Good written and verbal English language skills
  • Positive personality with good communication skills and team player
76

Comm System Design Engr Senior Resume Examples & Samples

  • 6) Must be able to obtain and retain DoD IAT Level II certification
  • 7) Prior Network administrator experience
  • 9) Final Transferable Secret clearance with a completed investigation within the last 5 years