Asic Digital Design Engr Resume Samples

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A Mayert

Austin

Mayert

4281 Ezequiel Garden

Boston

+1 (555) 600 8506

4281 Ezequiel Garden

Boston

Phone

p +1 (555) 600 8506

Experience Experience

Dallas, TX

Asic Digital Design Engr

Dallas, TX

Greenholt-Volkman

Dallas, TX

Asic Digital Design Engr

Prior knowledge CAD tool for development
Writing verilog and system-verilog test-benches. Performing functional coverage, assertion coverage, and code coverage
Be an individual contributor in the Design Tasks – RTL coding of design, debug, verification coverage improvement in the directed Verilog Test Bench, etc
A successful track record in project work
Design, implement, troubleshoot and/or debug FPGA based hardware prototyping systems
Knowledge of C
Knowledge of Perl/Shell scripts

Detroit, MI

Asic Digital Design Engr

Detroit, MI

Padberg, Homenick and Armstrong

Detroit, MI

Asic Digital Design Engr

Participate in test environment infra and regression infra development, testbench development in VMM/UVM/SystemVerilog/C++, test cases development and debug
Develop and execute verification for IP level functional features related to Interface IP system
Develop and maintain common methodology documentation and flow
The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide
Work closely with Design/Macro teams to identify the milestones and quality metrics of the project that includes scoping, tracking and delivery
Track standardization compliance efforts across IP development teams
Working knowledge of high speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus

present

Philadelphia, PA

Asic Digital Design Engr, Senior

Philadelphia, PA

Hahn-Christiansen

present

Philadelphia, PA

Asic Digital Design Engr, Senior

present

Create/ work on designs using Low Power Design Methodology
Perform various benchmarking and engineering testing tasks to improve overall product quality
Develop and execute functional test/verification plans
Perform constraint development and physical design activities
Defining place and route constraints, resolving STA issues and performing gate-level simulations
Managing, reviewing, and tracking the design and verification tasks executed by teams at off-site locations
Working knowledge of high speed interface protocols such as DDR, DFI, or memory subsystems

Education Education

Bachelor’s Degree in Engineering

Oregon State University

Bachelor’s Degree in Engineering

Skills Skills

Knowledge of high speed and low power design technique
Good communication skills
Understanding of key design and layout challenges at smaller technology nodes
Be familiar with schematic capture, spice simulation, LVS and DRC
Experience on SRAM memory design
Exposure to memory compilers will be
Exposure to FINFET technology nodes will be

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Asic Digital Design Engr Resume Examples & Samples

Strong desire to work with embedded processors or processor based systems · Knowledge of HDL design and ideally, RISC architectures
Understanding of programming at assembly and C/C++ level
Understanding of Hardware Verification Methodologies and best practices – Coverage Driven Verification, constrained random testing, VMM, eRM, OVM, UVM
Knowledge of Perl or other scripting languages for flow automation

Asic Digital Design Engr, Senior Resume Examples & Samples

Writing Verilog and System-Verilog test-benches. Performing functional coverage, assertion coverage, and code coverage
Generates documentation for circuit development, test plans, verification environments, and usage. May participate in evaluation and troubleshooting of digital and mixed signal circuits
Defining place and route constraints, resolving STA issues and performing gate-level simulations

Asic Digital Design Engr, Senior Resume Examples & Samples

Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as MIPI-I3C/UFS/Unipro/ SD/eMMC/ Ethernet/ USB/ AMBA (AMBA2, AXI)
Be an individual contributor in the Verification Tasks – Architecting and coding of TE, debug, verification coverage improvement, etc
Will contribute to technical review of TE Code of small and medium complexity
May contribute to technical process and quality improvement to achieve high quality deliveries
Will be expected to Solve complex/ abstract problems
The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment
The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide
May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers
Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc
Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro/ SD/eMMC/ Ethernet/ USB/ AMBA (AMBA2, AXI)
Hands on experience with creating detailed design of certain components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM/ VMM/OVM
Hands on experience with System Verilog/ VERA/ Specman coding and Simulation tools; Knowledge of C++/ OOPs Concepts
Knowledge of Perl/Shell scripts
Exposure to quality processes in the context of IP design and verification is an added advantage
Ability to work/ Prior experience as a Technical Lead for a small team is a major plus

Asic Digital Design Engr, Senior Resume Examples & Samples

Contributing to complex aspects of the project
Innovating and introducing new solutions and methods and their roll-out to peers
Communicating with management and senior personnel in other locations on matters requiring coordination across internationally located internal groups
Planning, scheduling and execution of projects
Bachelor degree in Electrical or Computer Engineering with 5+ years of experience, or Master degree with 4+ years of experience
Successful track record in project work
Previous experience in architecture of complex verification environment
Strong working knowledge in one or more of the following disciplines; SystemVerilog, UVM, OVM, VMM
Previous experience with Constrained Random Verification
Previous experience with SystemVerilog Assertions, Functional coverage and Test Plan specification
Advantageous to have either design, verification or protocol knowledge of high performance bus protocols such AXI and/or PCIe
INTMSJA

Asic Digital Design Engr, Senior Resume Examples & Samples

Develop and maintain IP subsystems including, specification, implementation and test
Help in driving the innovation of processor-based IP subsystems
Optimize designs for performance, speed, size and power
Interact with the verification, tools, modeling and simulation teams globally to deliver optimized solutions for our customers
Perform various benchmarking and engineering testing tasks to improve overall product quality
Keep abreast of state-of-the-art in Digital hardware Design methodology and tools
Guiding junior design engineers during product development
Master degree (or equivalent) in Electrical or Computer Engineering with 5+ years of experience
Significant experience in digital hardware design including activities such as RTL development, functional simulation, constraint development, synthesis, timing analysis, power analysis, behavioral modeling, etc
Experience / understanding of IC Design flows and good problem solving skills
Experience of Verilog design language
A good understanding of the integration of digital hardware components such as peripherals, bus interconnect, processors and memories
Good understanding of commonly used SoC interconnection protocols such as AMBA
Experience with design flow automation and scripting including Linux shell and Perl
Fluent In English, excellent communication skills

Asic Digital Design Engr, Senior Resume Examples & Samples

Development of functional verification environments (Test benches)
Development of test plans & test cases
Implementation of checkers, assertions, random test generators, high level transactional models and bus functional models (BFMs)
Performing simulation, random and focused stimulus generation and coverage analysis
Develop architecture and micro-architecture knowledge of the complex digital design block(s) under test
Experience: >= 5 Yrs. IMinimum 5 Yrs.)
Background in the pre-silicon verification of complex PHY IPs, ASIC or SoC designs
Experience with VMM, OVM/UVM and System Verilog
Experience with formal verification, System Verilog Assertions, code and functional coverage implementation and analysis
Experience with languages such as SystemC, Perl, TCL, Shell scripting
Experience with high speed Interface IPs such as USB3.1, PCI Express, .

Asic Digital Design Engr, Senior Resume Examples & Samples

Writing modular constrained-random verilog and system-verilog testbenches
Performing functional coverage,
Assertion coverage, and code coverage
Creating and tracking testplans
Analyzing failure cases and running gate-level simulations

Asic Digital Design Engr, Senior Resume Examples & Samples

Create/ work on designs using Low Power Design Methodology
May need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of small complexity functions/ product features for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/ USB/ SD, Multi-Media Cards/ AMBA (AMBA2, AXI)/ MIPI
Creates deliverables which do not require close review or supervision by a Senior Technical Lead
Hands on experience with creating micro-architecture/ detailed design from Functional Specifications for small/ medium design complexity. Must have worked on control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc
Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background
Knowledge of C

Asic Digital Design Engr Resume Examples & Samples

Be an individual contributor in the Design Tasks – RTL coding of design, debug, verification coverage improvement in the directed Verilog Test Bench, etc
May learn to do technical review of RTL Code of small/ medium complexity
The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs
Design of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc
Knowledge of one or more of protocols: Ethernet/USB/SD-MMC/AMBA (AMBA2, AXI)/ MIPI
Hands on experience with Verilog/ System Verilog coding and Simulation tools
Experience with Perforce or similar revision control environment

Asic Digital Design Engr Resume Examples & Samples

Hands on experience with System Verilog coding and Simulation tools
Prior ASIC/IP verification skills using UVM/ OVM or VMM methodologies, with essential knowledge of System Verilog
Knowledge of OOPs concepts, C++
Knowledge of one or more of protocols: Ethernet/USB/SDMMC/AMBA (AMBA2, AXI)/ MIPI
Experience with Perforce for revision control along with Perl/Shell scripts is a plus

Asic Digital Design Engr, Senior Resume Examples & Samples

Understand Standard Specifications/the functional specifications/feature enhancements/Design documents for the products for the DesignWare family of synthesizable cores in protocol areas such as USB/Ethernet/PCI Express/AMBA(AMBA2, AXI)/MIPI
Be an individual contributor in the Verification Tasks – Implementation of Test Environment/Verification IP enhancements, debug low to medium complex functional issues, verification coverage improvement, etc
Develop tests with specific scenarios, update tests, debug and fix medium complex functional issues in Verification IP or Test Environment
The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases, at least for small/ medium complexity features of the protocol/product specs
Work independently and create deliverables with minimal supervision by a Technical Lead
Must have BSEE in EE with 3+ years of relevant experience or MSEE with 2+ years of relevant experience in the following areas
Verification IP Development/Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc
Knowledge of one or more of protocols: USB/Ethernet/PCI Express/AMBA(AMBA2, AXI)/MIPI
Hands on experience in Verification IP or certain components of Test Environment coding, test case development and debug. The Test Environment must have used methodologies such as UVM/VMM/OVM
Hands on experience with System Verilog/ VERA/Specman coding and Simulation tools; Good Knowledge of OOPs Concepts

Asic Digital Design Engr, Senior Resume Examples & Samples

Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as USB/Ethernet/PCI Express/AMBA(AMBA2, AXI)/MIPI
Be an individual contributor in the Verification Tasks – Architecting and development of Test Environment/Verification IP, debug complex functional issues, verification coverage improvement, etc
Will contribute to technical review of Verification IP or Test environment code of high complexity
The candidate should be able to develop and analyze the coverage metrics and improve them with definition of additional test cases in CRV environment
May need to take the role of technical lead for a few of the components of the Verification IP or Test Environment and achieve high quality verification with a small team of verification engineers
Must have BSEE in EE with 10+ years of relevant experience or MSEE with 8+ years of relevant experience in the following areas
Hands on experience with creating detailed design of Verification IP or certain components of Test Environment from Functional Specifications/Test Environment Specifications. The Test Environment must have used methodologies such as UVM/VMM/OVM
Hands on experience with System Verilog/ VERA/Specman coding and Simulation tools; Strong Knowledge of OOPs Concepts

Asic Digital Design Engr, Senior Resume Examples & Samples

Design, verification and documentation for ASIC development
Architecture design, logic design, and system simulation,
Module interfaces/formats for simulation,
Knowledge of Verilog, System Verilog, and C/C++ programming,
Debugging software programs
Knowledge and experience of CAD tool development are required

Asic Digital Design Engr, Senior Resume Examples & Samples

Determines test bench design and test cases
Evaluates and exercises various aspects of the development flow which may include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics
Generates documentation for test plans, verification environments, and usage
Participate in evaluation and troubleshooting, debugging, running simulations of digital and mixed signal designs

Asic Digital Design Engr, Senior Resume Examples & Samples

Perform FPGA synthesis, define correct timing constraints, IO constraints to achieve time clean synthesis result
Will be involving all states of the prototype development process from the specification define, design implementation, simulation, FPGA synthesis, and hardware system verification
Must be proficient with Unix OS, Verilog HDL, Shell scripting
Hardware validation and debugging experiences are highly desirable
Knowledge of programming device driver in Linux/Windows system is plus
Knowledge of the PCIe/USB/AMBA Protocol or relevant high speed interface protocol (specifications, compliance and interoperability testing, design/verification experience etc.) will be a definite plus

Asic Digital Design Engr Resume Examples & Samples

Design, implement, troubleshoot and/or debug FPGA based hardware prototyping systems
A relevant degree in electronic engineering
Typically requires a minimum of 3 years of related experience

Asic Digital Design Engr, Senior Resume Examples & Samples

Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as UFS/Ethernet/ USB/ SD, Multi-Media Cards/ AMBA (AMBA2, AXI)/ MIPI
Be an individual contributor in the Verification Tasks – coding of TE, debug, verification coverage improvement, etc
Contribute to technical process and quality improvement to achieve high quality deliveries

Asic Digital Design Engr, Senior Resume Examples & Samples

Be an individual contributor in the Design Tasks – Architecting of medium complexity ASIC designs, micro-architecting, RTL coding of design, debug etc
Knowledge of one or more of protocols: MIPI-UFS/Unipro/Ethernet/USB/SD-MMC/AMBA (AMBA2, AXI)
Working knowledge of C

Asic Digital Design Engr Resume Examples & Samples

Develop and execute verification for IP level functional features related to Interface IP system
Work closely with Design/Macro teams to identify the milestones and quality metrics of the project that includes scoping, tracking and delivery
Participate in test environment infra and regression infra development, testbench development in VMM/UVM/SystemVerilog/C++, test cases development and debug
Provide technical direction to team members with respect to verification methodologies, verification environment capabilities, test planning, result analysis to enable the most effective verification flow
Verification experience of ASIC interface design or mix-signal system
Hands on experience with System Verilog/ VERA coding and Simulation tools; Knowledge of C++/ OOPs Concepts
Has Good analysis and problem-solving skills
Knowledge of Perl/Shell/Makefile scripts
Knowledge of Design for Verification and Design for LowPower
Team player with good communication skills of both verbal and written
Previous team or technical leadership experience on verification is a plus

Asic Digital Design Engr, Senior Resume Examples & Samples

Interact with and, in some instances, visit customers
Support DDR PHY integration, silicon bring-up and silicon debug activities
Participate in the generation of data books, application notes and white papers
Generate test benches and test cases
Perform RTL and gate-level SDF-annotated simulations
Perform constraint development and physical design activities
Assist test engineers with silicon evaluation
Develop and execute functional test/verification plans
Write synthesizable RTL code for circuit portions of integrated circuits

Asic Digital Design Engr Resume Examples & Samples

Evaluate and exercise various aspects of the development flow which may include such items as RTL lint and CDC checking, functional simulation, constraint checking, design for test logic, synthesis, timing analysis, power analysis, and verification coverage
Develop and maintain common methodology documentation and flow
Track standardization compliance efforts across IP development teams
Audit standards compliance for interface IP products
Confirm interoperability of PHY and Controller deliverables in a complete front-to-back flow (simulation, synthesis & implementation)

Asic Digital Design Engr Resume Examples & Samples

Knowledge of IC design flows
A successful track record in relevant project work
Good English communication skills
Capability to produce adequate technical documentation
Exposure to Verilog/VHDL
Exposure to System Verilog or VMM or OVM or UVM
Exposure to Unix, Perl and TCL scripting
Willingness to learn new things
Knowledge of MIPI or similar protocols would be advantageous