Asic / Layout Design Engineer Resume Samples
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Asic / Layout Design Engineer Resume Samples
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DM
D McLaughlin
Dell
McLaughlin
108 Foster Throughway
San Francisco
CA
+1 (555) 451 4783
108 Foster Throughway
San Francisco
CA
Phone
p
+1 (555) 451 4783
Experience
Experience
Chicago, IL
Asic / Layout Design Engineer
Chicago, IL
Rohan, Considine and Hessel
Chicago, IL
Asic / Layout Design Engineer
- Performs various in-depth performance/power analysis for current and future desktop, mobile and workstation products
- Work with immediate management to develop implementation schedules and track execution progress
- Strong working knowledge of D3D and OpenGL games and application benchmarks. Familiarity with Workstation and Adroid Applications is a plus
- Closely working with Design/Architecture/Verification team to develop new verification component
- Develops software tools to automate performance and power analysis, modeling and tracking process
- Working with leads to develop practical schedules
- Delivers useful 3D graphics performance resources to help identify potential performance bottlenecks in current and future benchmark applications
Houston, TX
MTS Asic / Layout Design Engineer
Houston, TX
Gleichner Inc
Houston, TX
MTS Asic / Layout Design Engineer
- Developing power and performance tests for power performance analysis in simulation environement
- Develop and execute test plans for system level functional features related to Memory Controller/ Power Management/ Coherency / Security / Multi-Media …etc
- Working with global 3D GPU architects to Investigate power and performance improvement features for next generation GPU chips
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency
- Maintain verification environment, solve flow issues, and develop scripts to improve flow efficiency
- Co-Work with World Wide Performance Verification and Design Team
- + Providing assistance to resolve synthesis, area, timing analysis, and power consumption issues
present
San Francisco, CA
Senior Asic / Layout Design Engineer
San Francisco, CA
Gutkowski Group
present
San Francisco, CA
Senior Asic / Layout Design Engineer
present
- 6- Flexible in working hours to accommodate working with co-workers in different time-zones
- Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager
- + Proficiency in Verilog, System Verilog, UVM, Perl, Unix shell scripting, makefiles and the make utility, and working in Linux and Windows environments
- Leverage existing test bench infrastructure as well as develop new components for performance verification
- Develop performance verification strategy, metrics and test plan
- + Create and maintain the block level test bench
- Working as the technical point of contact on the ASIC area
Education
Education
Bachelor’s Degree in Electrical
Bachelor’s Degree in Electrical
The University of Kansas
Bachelor’s Degree in Electrical
Skills
Skills
- + Good knowledge of Software Engineering and excellent programming skills
- Working in a team of design verification and design engineers, involved in all aspects of the verification flow from initial test planning to coverage and signoff closure under aggressive, market-driven schedules
- Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player
- Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality
- Building testbench components such as test libraries, models and BFMs by applying objected oriented design techniques and using advanced verification languages such as System Verilog, UVM and C++
- + Strong analytical thinking and problem solving skills with an excellent attention to detail
- Experience and strong knowledge of testbench development, industry standard bug tracking, and regression mechanisms, constrain random verification and coverage
- Good communication skills, strong interpersonal skills and the flexibility
- + ASIC design knowledge and ability to debug Verilog RTL code using simulation tools
- Strong analytical skills and attention to details
4 Asic / Layout Design Engineer resume templates
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1
Asic / Layout Design Engineer Resume Examples & Samples
- Be responsible for the multiple functional verification blocks of complex 3D Graphics IP cores for a combined CPU/GPU development effort (APU/Fusion)
- Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system
- Lead a more junior verification team
- Lead the documentation and executing of test plan(s) consisting of directed and constrained-random tests to be run during simulation
- Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects
2
Asic / Layout Design Engineer Resume Examples & Samples
- Generating RTL from specifications
- Logic design (Arbiters, FIFOs, Link Controllers, FSMs, TLB, caches, ...)
- Debugging complex designs
- Coding test-benches for design verification
- Leading-edge synthesis, static timing analysis, and formal verification
- Debugging complex system-level simulations
- Linting RTL and checking clock-domain crossings
- Emulating designs on FPGA-based systems
- Working with leads to develop practical schedules
3
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Hands on experience in large scale ASIC chip physical design
- Successfully gone through several complete product development cycles
- Good listening, writing and speaking English
- LI-ZY1
4
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Contribute to the verification of several critical high speed digital designs at the IP level test bench
- Will be involved in all aspects of the verification flow from initial test planning to coverage and signoff closure
- 1-to-4 years of industry experience in ASIC Design Verification with a focus on IP verification. New graduates are also welcome
- Strong knowledge in object oriented programming, data structures, and algorithms
- Must have excellent system debug skills
- LI-MA1
5
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Experienced in physical design flow
- Good programming skill with tcl, perl or python
- Plus with 3+ projects tapeout experience
6
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Working with SoC design team to deploy DFT/DFD IP design to SoC projects using architectural specifications and design construction flows
- Planning and communicating DFT/DFD IP integration status to project management
- Performing RTL integration/insertion, synthesis, equivalency checking, timing analysis and closure including defining constraints
- Deploying DFT scan and memory-BIST insertion flows to SoC projects, which includes flow bring-up, qualification, debug and training end-users
- Collect feedback from SoC team and suggest improvements to IP design and deployment flows
- Providing DFT/DFD feature bring-up and pattern debug support to Product and Platform Engineering teams during first silicon bring-up, qualification and failure analysis
7
Asic / Layout Design Engineer Resume Examples & Samples
- Verification of Graphic North Bridge design using random methodologies – Test Planning, Implementation and Execution
- Integration of random modules to various testbenches
- Flexible in terms of responsibilities and hours
8
Asic / Layout Design Engineer Resume Examples & Samples
- Hands on experience in physical design is a plus
- Familiar with Unix/Linux environment
- Familiar with Back-End (physical design) EDA tools is a plus
- Good at scripts is a plus
9
Asic / Layout Design Engineer Resume Examples & Samples
- Good at ca/ca++, pearl, familiar with systemic, pi, make is a plus
- Familiar with RTL coding and front-end design flow
- Good communication skills and fluent English
- Strong responsibilities and team spirit
10
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Working with architects and leads to understand features to be implemented and verified
- Design documentation creation
- Design creation using Verilog to optimize performance, area, and power
- Initial verification and debugging test failures
- Specifying cover points, reviewing functional and code coverage results and assisting to increase coverage
- Providing assistance to resolve synthesis and timing analysis issues
- You might also be responsible for new architecture discussion and RTL implementation
11
MTS Asic / Layout Design Engineer Resume Examples & Samples
- IP verification and deployment of Ethernet IP for AMD SoC chips
- Define IP verification strategy, Testplan, Testbench structure
- Build/Debug Testbench/testcases with UVM/SystemVerilog to achieve verification goals
- Maintain verification environment, solve flow issues, and develop scripts to improve flow efficiency
- Proven IP / SoC Verification / Deployment Experience
- Must have strong background on IP verification/deployment
- Enthusiasm on technical topics
- Must be proficient in SystemVerilog/UVM coding, debugging and modeling
- Deep understanding of below technical aspects would be an asset
- 10GbE+ MAC/PHY IP/Subsystem verification
12
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Responsible for delivering RTL designs of world-class critical IP components in a robust and modular manner, working closely with micro-architects, verification and other teams including third party vendors
- Expected always improving design mind-set to improve existing RTL design by applying cross design clocking, low power design, and other techniques
- Responsible for delivering high quality RTL that meets timing, LINT, CDC and other requirements
- Will be involved in many aspects of the design implementation process, which may include but not limited to, debug, verification, conducting design, code and test plan reviews
- 5 – 10 years of industry experience in high speed and low power ASIC Design
- Must have a strong background in all aspect of ASIC implementation, such as RTL Verilog development, synthesis flows, static timing analysis, multi synchronous design, RTL Linting tools, equivalence checking
- Must have excellent simulation debug skills
- Knowledge of x86 and ARM system architecture
- Experience in silicon bring up and debug
- Experience with scripting languages like Ruby and Perl a plus
- Good understanding of object oriented programming, C/C++, System Verilog, UVM and Perl
- Mentoring experience
- Highly motivated and proactive individual
13
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Construct IP performance models
- Develop performance verification strategy, metrics and test plan
- Analyze simulations results and present results to design and architecture teams
- Leverage existing test bench infrastructure as well as develop new components for performance verification
- Execution on test plan
- Opportunities to contribute NBIO system architecture
- Potentially lead a small team executing towards project deadlines
- 6 – 10 years of industry experience in performance modeling and/or performance verification
- Good understand of I/O subsystem architecture including buses and interconnects, I/O device behavior towards system memory, interrupts and software device drivers
- Experience with performance verification
- Good understanding on RTL verilog
- Working knowledge of industry standards such as PCIe, AXI, IOMMU and SMMU
14
Asic / Layout Design Engineer Resume Examples & Samples
- Co-Work with World Wide Performance Verification and Design Team
- In post-silicon
- Master with 3+ years or Bachelor with 7+ years of industrial experience of GPU or CPU
15
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Working with global 3D GPU architects to Investigate power and performance improvement features for next generation GPU chips
- Quantifying power and performance improvement in popular benchmark and game applications (like 3D Mark, Firestrike, Battleman, etc.) with state-of-art modeling methodology
- Developing power and performance tests for power performance analysis in simulation environement
- Feedback and driving key architectural decisions such as cache size, clock frequency, chip level power domain partition, etc
- Working with product team for product definition and trad-offs
- Need work in a collaborative environment with global engineering teams
- Master degree or above in EE or CS
- Strong knowledge in ASIC/SoC design and common SoC architecture
- Knowledge in SoC performance analysis like bandwidth, latency, etc
- Proficient in Verilog, C, C++
- Good skills in data analysis
- Good communication skills is a must
- Knowledge in 3D algorithm or low power design is a plus
- Knowledge in SoC level verification methodology is a plus
16
Asic / Layout Design Engineer Resume Examples & Samples
- Engineering (CS or EE) with advanced computer architecture course completed preferable
- Requires strong programming skills
- Requires exposure(via classroom or other work experience) to with Verilog, System Verilog, Object Oriented Programming/C++, Perl, and logic simulation
- Experience with UVM is a plus
- Requires very strong understanding of computer architecture
- Requires strong communication skills and the ability to work independently
17
Asic / Layout Design Engineer Resume Examples & Samples
- Work with Chip/IP architect to define macro-architecture specification for sub-blocks (optional)
- Implement RTL coding and communication with verification team to achieve good coverage (optional)
- Be responsible for synthesis/LEDA/CDC/LEC at both IP and SoC level
18
MTS Asic / Layout Design Engineer Resume Examples & Samples
- MSEE with 9+year or BSEE with 11+ years of industry experience in deep submicron ASIC design
- Expertise with HDL and design of high speed and high complexity digital logic required
- Expertise of Computer Architecture and computer Arithmetic
- Expertise of Computer Graphic and HW implementation
- Experience with SOC Integration and Place and Route(a plus)
- DDR-SDRAM/PCI/PCI-e experience(a plus)
19
Asic / Layout Design Engineer Resume Examples & Samples
- Master in Electrical or Computer Engineering
- Familiar with Linux Environment (including shell scripting and linux gnu tools)is a plus
- Good at C/C++, Perl, Makefile, familiar with Ruby, SystemVerilog, SystemC is a plus
20
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Participate IP and SoC level design and verification work
- Simulate and debug the codes in coding stage
- Write ASIC specific part of test plan. Co-work with FPGA/verification engineers to prove functional correctness from block level to SoC level
- Support Firmware bring-up and debugging
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency
- Be proficient in C/C++/SystemVerilog experience
- Will be a plus if having FPGA validation experience
21
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Deep understanding on ASIC/SOC design flow
- Excellent knowledge of design verification methodology, such as UVM or OVM/VMM
- Solid experiences with simulation model creation and the testbench build
- Strong RTL coding with Verilog
- Be good at scripting language, such as Perl, C shell, Makefile
22
Smts Asic / Layout Design Engineer Resume Examples & Samples
- Minimum 7 years of proven verification experience of complex CPU/ASIC projects
- Demonstrated mastery of successful verification from test planning till tapeout
- Proven developer of complex verification checkers and stimulus using OVM/UVM or equivalent
- Experience writing and closing functional coverage on complex functions (1000s of gates)
23
Smts Asic / Layout Design Engineer Resume Examples & Samples
- Working with Graphics Architects and Design Team to Define Forward-Looking Power Management Features
- Feature Documentation and Review Preparation
- Test Creation, Verification, and Debugging of Graphics Features
24
Asic / Layout Design Engineer Resume Examples & Samples
- Familiar with EDA tools and at least one script in linux environments (perl/python/cshell/...)
- Knowledge of 3D pipeline, computer graphics, computer architecture and operating system is a plus
- Strong skills in problem solving, communication and team work
- Good oral/written English skills
25
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Understand functionality of design in architecture and design specifications. Write the functional validation part of test plan from block level to SoC level to achieve the functional coverage requirements
- Deliver bug-free C-model from algorithm level to cycle level
- Be responsible for test case composition, testbench and test environment setup, test automation tool development, and BFM model coding and debugging
- Support testing for DFx and FPGA
- Apply necessary verification methodologies to ASIC design, such as coverage, assertion, randomization, gate-sim etc., and achieve the verification goals
- Support FW/SW bring-up and debugging
- Must have strong background on video codec / processing algorithms
- Must be proficient in C++ programming and debugging in Linux and Windows platforms. Know well about SW engineering
- Must be skillful in shell/perl/tcl/makefile programming in Linux OS
- Should have adequate ASIC design knowledge and be able to debug RTL codes using corresponding tools
- It’s a plus if having Tape-Out experience
- It’s a big plus if have Computer Vision experience
26
Smts Asic / Layout Design Engineer Resume Examples & Samples
- Major in EE, CS or related, Master Degree with 6+ years or Bachelor with 8+ years working experiences
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Should have excellent communication skills (both written and oral)
27
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Minimum of 3 years of experiences on architecture design, HW design or performance analysis
- Plus with experience on CPU/GPU Design/Verification
- Plus with 2+ years’ Linux/Shell
28
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Must be professional in C++ programming and debugging in Linux and Windows platforms
- Must have deep understanding on SW engineering
- Must be experienced in various verification methodologies from block level to SoC level, and familiar with corresponding tools
- Must be skillful in shell/perl/tcl/Makefile programming in linux OS
- Must be familiar with mainstream simulation/coverage/randomization tools
- Should have the knowledge of system Verilog
- Will be a big plus if have strong background on video codec / image processing algorithms
29
Asic / Layout Design Engineer Resume Examples & Samples
- MSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASIC design
- Expertise in place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, timing closure
- Successfully gone through complete product development cycle. Good analytical and debugging skills
- Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player
- Familiar with Back-End (physical design) EDA tools (synopsys,cadence,magma)
- Familiar with Front-End EDA tools or circuit design is a plus
30
Asic / Layout Design Engineer Resume Examples & Samples
- Master Degree in electrical engineering with 1+ years of digital circuit design and logic design experience; Or Bachelor Degree with 3+ years related working experience
- Verilog and logic synthesis
- Design knowledge of high-speed datapath and state machines
- Experience with Integration and Place and Route(a plus)
- Computer Architecture and computer Arithmatic (a plus)
- Computer Graphic Basic knowledge(a plus)
- MSEE with 3+year or BSEE with 4-6 years of industry experience in deep submicron CMOS full chip design and functional verification
- Expertise with HDL and design of high complexity digital logic required
- Expertise with industry standard tools such as VCS/NCSIM, synthesizer, LEC etc required
- Expertise in design and verification of high speed memory control systems
- Familiar with the high performance memory interface including DDR1/2/3 SDRAM
- Knowledge if IO pad, timing and signal integrity on board is plus
- Experience of chip debug of memory system is a plus
31
Asic / Layout Design Engineer Resume Examples & Samples
- Understand the ASIC design/verification flow and help design/verification engineers to accomplish targets
- Develop infrastructure and environment for SOC/IP level chip design verification
- Closely working with Design/Architecture/Verification team to develop new verification flow
- Major in EE, CS or related, Master Degree or Bachelor with 3+ years working experiences
- Familiar with Linux Environment (including command shell scripting)
- Skillful at script language like ruby, perl, or tcl
- Be good at C/C++ programming
- Good knowledge on verification methodology
32
Asic / Layout Design Engineer Resume Examples & Samples
- Develop micro-architecture specification for GPU blocks
- Develop RTL code for GPU blocks in Verilog HDL
- Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design
- Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology
33
Engineer Asic / Layout Design Engineer Resume Examples & Samples
- Lead Performance Verification and Analysis for new chip
- Master with 5+ years or Bachelor with 7+ years of industrial experience of GPU or CPU
- Minimum of 3 years of experiences on hardware performance/function analysis
- 3 + year experience on C\C++
- Plus with 3+ years’ OpenGL/D3D driver experience
- Plus with 2+ years’ perl/python
- Proficient in English read/write/speaking/listening
34
Asic / Layout Design Engineer Resume Examples & Samples
- Understand system architecture & specifications. Write the macro architecture spec and block spec for video IPs
- Be responsible for RTL coding & RTL delivery according to the spec
- Be responsible for RTL synthesis and related front-end flow
- Be responsible for block verification and support IP verification
- Working as the technical point of contact on the ASIC area
- Must be proficient in RTL coding under Linux platforms. Know well about verification methodology
- Should have adequate in shell/perl/tcl/makefile programming in Linux OS
- It’s a plus if having Tape-Out & Bring-up experience
- It’s a plus if having Video Codec or ISP experience
35
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Create and execute SoC testplan including data-path and interrupt, virtualization, security, power management, etc
- Support integration and qualification of all the IPs for SoC
- Help to improve DV environment building flow
36
Asic / Layout Design Engineer Resume Examples & Samples
- A truly multidisciplinary function, working in close collaboration with the design managers and Directors on the various efforts involved in the definition and implementation of projects and scoping development efforts and project schedules
- Responsible for the overall chip verification, in addition to the possibility of direct responsibility for the architecture of testbench and infrastructure
- Interacting with and guiding a wide variety of internal and external design verification development teams, DV methodology, Silicon IP and tool vendors
- Work with architects, and the design and DV team to define develop Testplan and execute system verification plan from power management, system features e.g. FSA, Security, Coherency, etc
37
Principal Asic / Layout Design Engineer Resume Examples & Samples
- Implementation of new design and verification methodologies, such as
- Must be proficient in C++, SystemVerilog, UVM, Scripting Languages, Verilog/VHDL, make/gmake, HTML, TCL/TK, PHP and debugging in Linux and Windows platforms. Good knowledge of Software Engineering practices
- Must have graphics pipeline experience (College course using OpenGL/OpenCL/DX may be sufficient)
- Must have previous design or verification experience
38
Asic / Layout Design Engineer Resume Examples & Samples
- Be responsible for the multiple functional blocks of the complex 3D Graphics IP cores for a combined CPU/GPU development effort (APU and dGPU). RTL and DV skills are recommended
- Be part of a team of designers and verification engineers, working closely with other team members to implement and verify the functionality of a given design element within the context of the block, chip and overall system as well as to design features for the next generation in RTL
- Lead a more junior team members
- Be expected to adopt the evolving verification and design methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects
39
Senior Asic Layout / Design Engineer Resume Examples & Samples
- Design verification (test plans, test cases, developing automation suites)
- Coding simulations and test benches
- Writing complex SV and C/C++ models
- Debugging large system-level simulations
- Resolving silicon bring-up issues
40
Asic / Layout Design Engineer Resume Examples & Samples
- RTL design in Verilog
- Synthesis with timing driven placement and design for power (DFP)
- Formal verification of synthesized netlists
- Clock domain crossing (CDC) analysis
- Three or more years of ASIC design experience (outside university)
- Experience with RTL coding in Verilog
- Significant experience with standard ASIC design tools (synthesis, simulation, equivalence checking, static timing analysis)
- Thorough understanding of ASIC design flow
- Strong knowledge of scripting, Linux/Unix environment
- Basic knowledge of physical design (PD) process
- Strong organization and multitasking, as well as problem solving and analytical skills are a must
- Must be a self starter and able to independently drive tasks to completion
41
Asic / Layout Design Engineer Resume Examples & Samples
- BS degree in Electronics or Computer Engineering with 0 to 3 years of experience or BS + MS degree with 0 to 2 years of experience
- Proficient in Verilog, C++, System Verilog and Object Oriented Programming techniques
- Familiarity with ASIC Design flow
- Experience with Design Verification methodologies including UVM, OVM or VMM is a plus
42
Asic / Layout Design Engineer Resume Examples & Samples
- Develop architectural/functional models for processor, graphics, IO peripherals and other IPs
- Develop functional test plan and tests for architectural models
- B.S or higher in Computer Engineering or Computer Science
- Experience in system software development in C++ in Windows and/or Linux environments
- Understanding of x86 or ARM architecture
43
Asic / Layout Design Engineer Resume Examples & Samples
- Work with architecture/IP designers to get a full deep insight on the design under test
- Test case create/triage to ensure complete coverage
- Candidate is preferred to be MSEE with minimum of 2 years, or BSEE with minimum of 4-year experience in digital ASIC/SOC design verification
- Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC (Strong knowledge of SoC integration technique and methodology )or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort) or multimedia/video is preferred
- Good knowledge of SystemVerilog and OVM is a plus
- Good knowledge of Verilog/C/C++/System C/SystemVerilog
- Verification insights into random techniques
- Strong knowledge of low-power design technique and implementation flow
- Verification of Virtualization Components is an asset
- Strong C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience
- Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)
- Familiar with ASIC EDA tools, i.e. DCT, Primetime, Formality, Z-in…
- Proficient in STA and multiple clocking design
- Strong cooperation skill with global team
- Good at English for communication in talking/writing/reading
- Experience of team lead is plus
- Experience of tape-out using 40nm or advanced technology is plus
- Technical publication/paper, i.e. SNUG is plus
- Strong self-motivation
- Be open, passion and capability to work under high pressure
44
Experienced Asic / Layout Design Engineer Resume Examples & Samples
- Excellent analytical and problem solving skills along with attention to details
- Strong Timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding
- Hands on experience in taping out 28nm, 32nm, and/or 40nm SOC
45
Engineer Asic / Layout Design Engineer Resume Examples & Samples
- Participate graphics verification and methodology work
- Drive functional/performance/low power verification with state-of-the-art techniques
- Develop verification framework based on Ruby
- Improve current verification solutions with leading-edge initiatives in block/IP/SOC level
- Be proficient in C/C++ or Ruby experience
46
Asic / Layout Design Engineer Resume Examples & Samples
- Building testbench components such as test libraries, models and BFMs by applying objected oriented design techniques and using advanced verification languages such as System Verilog, UVM and C++
- Will be responsible for feature verification using both coverage driven random and directed testing techniques
- 0-to-3 years of industry experience in ASIC Design Verification with a focus on IP verification. New graduates are also welcome
- Must have hands-on experience with Verilog, System Verilog, C/C++, UVM/OVM and Perl
- Must have experience and strong knowledge of testbench development, industry standard bug tracking, and regression mechanisms, constrain random verification and coverage
- Working knowledge of industry standards such as PCIe, HyperTransport, AXI, IOMMU and SMMU
47
Asic / Layout Design Engineer Resume Examples & Samples
- Working in a team of design verification and design engineers, involved in all aspects of the verification flow from initial test planning to coverage and signoff closure under aggressive, market-driven schedules
- Responsible for feature verification using both coverage driven random and directed testing techniques
- 0-to-2 years of industry experience in ASIC Design Verification with a focus on IP verification. New graduates are welcome
- Hands-on experience with Verilog, System Verilog, C/C++, UVM/OVM and Perl
- Experience and strong knowledge of testbench development, industry standard bug tracking, and regression mechanisms, constrain random verification and coverage
- Strong analytical skills and attention to details
48
Asic / Layout Design Engineer Resume Examples & Samples
- Performing DFT/DFD RTL design using architectural specifications and AMD design flows
- Performing RTL implementation, integration/insertion, synthesis, equivalency checking, timing analysis and closure including defining constraints
- Writing and maintaining DFT/DFD documentation and specifications
- Verifying block-level or chip-level DFT/DFD features in a large ASIC design
- Test plan creation and test development
- Stimulus writing and debug, and regression clean-up
- Performing scan ATPG/DRC, pattern generation and simulation
- Delivering production quality ATPG patterns to operations engineering team
- Providing DFT/DFD feature bring-up and pattern debug support to operations engineering team during first silicon bring-up, qualification and failure analysis
- Creating software, scripts and other support technology to enable successful creation of the items above
- Working with a multi-discipline and international team of engineers
- Understanding various technologies that must work with DFT/DFD technology such as CPU’s, Graphics engines, memory and I/O controllers, etc
- Candidate must have minimum B.Sc in Electrical or Computer Engineering (or equivalent)
- Good understanding of computing/graphics design architecture
- Familiar with ASIC design, fabrication, assembly and ATE test
- Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST is a plus
- Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
- Familiar with verilog design language, Verilog simulator and waveform debugging tools
- Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus
49
Asic / Layout Design Engineer Resume Examples & Samples
- Working with Senior Hardware Designers to understand features to be implemented and verified
- Estimating the performance, area, and power impact of the new features
- Specifying cover points; reviewing functional and code coverage results and assisting to increase coverage
- Must have a BS degree in Electrical or Computer Engineering (MS degree preferred)
- Must have 2+ years of experienced in RTL level ASIC design
- Must be proficient in Verilog, SystemVerilog, and have experience with EDA tools e.g. Mentor/Cadence
- Must have strong analytical thinking and problem solving skills, and excellent attention to detail
- Must have excellent English oral and written communication skills
- Must have excellent teamwork and interpersonal skills
- Experience with programming languages: C/C++, Perl, TCL, UNIX shell scripting, Makefile
- Experience in OVM/UVM and have a working knowledge of creating/modifying Verilog testbenches
50
Asic / Layout Design Engineer Resume Examples & Samples
- Development of verification environment and infrastructure
- Development of directed and random verification tests to validate IP/chip function
- Debug of Verilog RTL and gate-level simulation, at the IP and/or chip-level
- Verification functional coverage using industry standard coverage analysis tools/methods
- Replicate functional issues found post-silicon; review/enhance tests to verify bug fixes
51
Asic / Layout Design Engineer Resume Examples & Samples
- Tasks include RTL synthesis, Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off
- Ability to solve technical problems independently with little or no help
- Communicate effectilvely with cross functional teams to resolve issues in timely manner
- Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
- Must be a self-starter, and be able to independently and efficiently drive tasks to completion
- Ability to provide mentorship and guidance to junior engineers, and be an effective team player
52
Asic / Layout Design Engineer Resume Examples & Samples
- Define and execute the functional test plan and verification strategy for specific IP on pre and post-silicon
- Work closely with supporting teams in design, diagnostics, emulation, firmware, and driver to ensure readiness for first silicon arrival
- Debug issues found during emulation, bringup, validation, and production phases of the program
- Leading collaborative technical discussions to drive resolution on technical issues
- Strong debug and problem solving skills
- 5-10 years of related industry experience
- Knowledge of 3D GFX technology and IP an asset
- Experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc
- In-depth knowledge of PC architectures and other (Display, memory, USB, etc.) interfaces an asset
- Leadership and mentoring skills a definite asset
- Must be a self starter and be able to independently drive tasks to completion
53
Asic / Layout Design Engineer Resume Examples & Samples
- Integrate functional IPs into SoC per architectural requirement
- Develop RTL code for macro blocks in Verilog HDL and make sure functional correct and reusable for different configuration
- Participate in making functional/technology based chip targets in timing, area, power. Develop timing constraint, power intent spec accordingly
- Synthesis and deliver qualified netlist, cowork with PD to settle chip floorplan and achieve timing closure
54
Asic / Layout Design Engineer Resume Examples & Samples
- Digital design and RTL coding for various functional blocks related to power management, clocking and security
- Contributing to micro-architecture of digital blocks, hardware/firmware partitioning
- Occasional creation of utility software in using C++, perl, php
55
Asic / Layout Design Engineer Resume Examples & Samples
- Responsible for block level RTL design implementation, synthesis, LEC, Lint etc
- Interface with system architects to translate high level feature and performance requirements into micro-architecture and design specifications
- Coordinate implementation of block level verification and C-model emulation
- Collaborate with Physical Design teams for design timing closure
- Collaborate with ASIC integration teams for timely delivery of design into ASIC/SOC environment
- Cooperate with graphics core and SOC verification teams for functional and performance verification of the block
- Support post-silicon bring-up activities leading towards ASIC production release
- Ensure that all project deliverables for the block are met in a timely manner
56
Asic / Layout Design Engineer Contractor Resume Examples & Samples
- Build reusable test bench components such as test libraries, models, BFMs and checkers by applying objected oriented design techniques and using advanced verification languages such as System Verilog, UVM and C++
- Will be involved in all aspects of the verification flow from test bench architecture, test planning to coverage and signoff closure
- Collaborate with AMD’s Central Verification Methodology team to develop, evaluate and deploy new tools, flows and verification IP
- 1-to-3 years of industry experience in ASIC Design Verification with a focus on IP verification
- Strong knowledge in object oriented programming, data structures and algorithms
- Experience in performance verification and modelling as plus
- Working knowledge of industry standards such as PCIe, AXI, USB, or similar a plus
57
Asic / Layout Design Engineer Resume Examples & Samples
- Write the block level test plan
- Create and maintain the block level test bench
- You might also be responsible for the creation of C models for a portion of the design
58
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Involves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiatives
- Is required to deal with internal groups on behalf of the group or project
- Has accountability for results in a particular area of work
- May have limited accountability for a small number of engineers related to projects (2-5),
59
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Writing design documentation
- Estimating the impact of the new features on the area and power of the block
- Design creation using Verilog and System Verilog to optimize performance, area, and power
- Providing assistance to resolve synthesis, area, timing analysis, and power consumption issues
60
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Hands on experienced in STA and technique for timing closure
- Power and signal integrity analysis
- In-depth knowledge of Synopsys P&R EDA tools/design flows
- Finfet experience is a plus
- Experience in full chip integration
- Experience in scripting with TCL, Perl or Python
- Good writing, reading and listening skills in English
- Good communication skills with strong interpersonal skills with flexibility
- 4+ years of production project tapeout experience of multi-million gate design
61
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Hands on experienced in EDA tools like Encounter / Innovus and ICC2
- Hands on experience in top level floorplanning
- Understanding of floorplan and layout techniques for foundry rule compliant
- Good writing, reading and listening skills
- 3+ years of projects tapeout experience
62
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Represent NBIO team on SOC global convergence meetings
- Deploy NBIO contains into various SOC and provide techinical consultation to SOC team
- Subsystem level test plan development and SOC test plan consultant
- Subsystem level test bench setup/maintain, methodology deployment, verification component create/maintain
- Deploy NBIO or provide technical consult support to SOC teams
- Candidate is preferred to be MSEE with minimum of 5 years, or BSEE with minimum of 7-year experience in digital ASIC/SOC design verification
- Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort) or multimedia/video is preferred
- Verification of large scale ASICs
- Experience in power verification is an asset
63
MTS Asic / Layout Design Engineer Resume Examples & Samples
- MSEE with 5+year or BSEE with 8+ years of industry experience in deep submicron ASIC design and verification
- Expertise of Computer Architecture and computer Arithmetic (a plus)
- Expertise of Computer Graphic and HW implementation(a plus)
64
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Bachelors degree in Electrical or Computer Engineering and 6 years Physical Design experience or Masters degree and 4 years experience
- Excellent communication and problem solving skills
- Excellent UNIX and scripting programming skills (Perl, Python and/or TCL)
- Strong understanding of digital circuits
- Experience with flow automation
- Expert knowledge of at least one EDA place & route tool (Cadence Innovus, Synopsys IC Compiler II, Mentor Olympus, ATopTech Aprisa)
- Experience with version control software (e.g. perforce, git)
- Highly motivated, self-starter with good interpersonal skills
65
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Software modeling (in C++) of the next-generation graphics architecture
- Verification of the software model (both unit/block level testing AND graphics core testing)
- Supporting the build flow for the software model and improving runtime on multiple operating systems, including LINUX and Windows
- Supporting the use of the software model in our RTL verification flow, including debugging of software model and the RTL code where there are mismatches between the results generated from the two models
- Supporting running state-of-the-art game traces on the software model to collect performance and power statistics to support critical decision making for new architecture changes
66
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Working with sub-system architects to understand sub-system power consumption of current features and features to be implemented, and how they fit within a given power budget
- Design changes using Verilog to optimize power, performance, and performance per watt
- Microcode development in assembly language to analyze workload bottlenecks and apply power where needed
- Initial verification and debugging test and power regression failures
67
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Development and execution of pre-silicon verification test plans
- Verification of complex microprocessor SOC's
- Knowledge of industry standard simulation tools (VCS, Verdi)
68
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Develop assertions and coverage points for the major interfaces
- Develop the testbench and the associated libraries used in logic simulations
- Help debug simulation failures
- Create the documentation and user guide for verification components
- Bachelors or Masters degree in Electrical or Computer Engineering
- 2 - 5 years of ASIC design/verification experience
- Strong knowledge of object oriented design verification techniques, and ASIC design fundamentals
- Knowledge of ASIC or PC architecture and the digital design design/flow concepts
- General understanding of hardware and software interaction within a system
- Good working knowledge of UNIX, Linux, Windows
- Proven debugging and problem analysis skills
69
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Technical lead of five to eight senior level engineers
- Tasks to include Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off
- Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction
- Drive and hands-on flow development and scripting
- Technical and schedule discussion with multi-site engineers and managers
- Strong communication, Time Management, and Presentation Skills
- Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player
70
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Work closely with the SoC design team on understanding the CPU/APU system features being designed
- Design, implement and improve verification testbench in Verilog, System-Verilog, C/C++, OVM
- Develop and refine test libraries, model and test cases
- Apply functional coverage/assertion into testbench as enhancement
71
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Participate in SOC full Chip DV feature and architecture definition
- Implement SOC DV functions including Infrastructure, METHODOLOGY, tools, functional / Performance / Power verification,
- Perform verification testplan
- Perform coverage (code and functional), debugging,
72
Senior DFT Asic / Layout Design Engineer Resume Examples & Samples
- Basic knowledge of ASIC/SOC design flow, including coding, simulation, verification, synthesis and STA
- Familiar with TetraMAX , DFT Compiler tool
- Good English communication skill and team work
- Fast learning and hard working
73
Pmts Asic / Layout Design Engineer Resume Examples & Samples
- BS/MS in EE/CS with 10+ years of hardware verification and management experience
- Experience developing cycle-accurate hardware performance models in a high-level language, such as C++
- Experience using hardware performance models to analyze bottlenecks and to find optimizations in computer architecture features
- Experience working in hardware and software realms
- Working knowledge of languages such as C/C++/Verilog/SV/UVM/Python/Perl etc
- Familiarity with design flows and methodologies used for chip verification
- Capable of managing small technical teams
- Highly organized, able to prioritize and juggle multiple work streams to tight deadlines
74
Smts Asic / Layout Design Engineer Resume Examples & Samples
- MS/PhD in EE/CS with 5+ years of hardware verification experience
- Knowledge of SOC and system architecture and familiar with RTL designs/Coding styles
- Experience managing technical teams is a plus
- Familiarity with X86 Assembly is a plus
75
Smts Asic / Layout Design Engineer Resume Examples & Samples
- Develop tools/flow for the AMD verification environment
- Test-drive and qualify vendor tools and integrate them into the AMD environment
- Develop verification components for the major interfaces, for driving the stimuli, monitoring internal interfaces, and capturing the output from the DUT (design under tests), using SystemVerilog (UVM), Verilog or C++
- Define and develop the randomization methodology and strategy used in logic simulations
- At least 5 - 7 years of ASIC design/verification experience
- Knowledge of industry bus interfaces, such as the AXI AMBA bus
76
Smts Asic / Layout Design Engineer Resume Examples & Samples
- Be responsible for a new functional block of the complex 3D Graphics IP cores for a combined CPU/GPU development effort (APU and dGPU). RTL and DV skills are required
- Lead the documentation and executing of any features that the candidate is assigned to; in terms of design and DV
- Also be proficient in hardware modeling and/or assertion-based verification methods
77
MTS Asic / Layout Design Engineer Resume Examples & Samples
- Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
- Generate DFT related timing constraints and work with PD team for timing closure
- Participate in ATE bring-up and debug the DFT patterns on ATE
- Design and implement other DFX (debug, characterization, yield etc) logics
78
Smts Asic / Layout Design Engineer Resume Examples & Samples
- BS degree in Electronics or Computer Engineering with at least 8 years of experience or BS + MS degree with at least 6 years of experience
- Expert in RTL Design techniques and methodologies as well as Formality, Timing, Synthesis and CDC
- Proficient in Verilog, Perl, C++ and System Verilog
79
MTS Asic / Layout Design Engineer Resume Examples & Samples
- MS/PhD in EE/CS with 8+ years of hardware verification experience
- Demonstrated technical expertise in functional verification of microprocessor/ASIC designs
- Experience managing technical teams
80
Smts DFT Asic / Layout Design Engineer Resume Examples & Samples
- Solid knowledge on DFT design, including JTAG, IEEE1500, MBIST and ATPG
- Verilog coding experience
- Perl, TCL, Makefile coding experience
- Experiences as technical leader
81
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
- Responds to NBIO IP netlist release flow, includes synthesis, CDC, Leda, formality, DFP, Vsi
- Responds to NBIO IP post-timing closure support by working with physical design team
- Responds to NBIO IP ECO manual ECO at gate level
- Responds to NBIO netlist quality sign-off for each milestone
82
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Major in EE, CS or related, Master Degree with 5 years working experience or Bachelor with 7+ years working experience
- Be familiar with VerilogHDL or digital circuit design is required
- Be familiar with one or more ASIC flows (synthesis, formal verification,timing analysis, Place and Route, floorplan, physical verification, etc.) and usage of related EDA tools
- Good programming skill with one or more languages (e.g. Tcl, Perl, python, c/c++, etc.) in Unix/Linux and a strong desire to automate flow
83
Senior Asic / Layout Design Engineer Resume Examples & Samples
- 1- Writing/Implementing/Reviewing Test Plans
- 2- Developing Verification Components for Re-Usable Verification IP in SystemVerilog
- 3- Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries
- 4- Analyzing Functional, Code, and Test Plan Coverage
- 5- Implementing Assertions, Checkers, and Monitors
- 6- Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools for Design Verification
- 7- Deploying Industry-Leading Verification Methodologies such as UVM
- 8- Triaging and Debugging Regressions
- 9- Replicating In-Silicon Bugs with Directed Simulations
- 10- Conducting and participating in Code Reviews
- 3- Drives to learn and perform at his or her highest potential in a technical capacity
- 4- Thrives in both a team environment and in individual contribution
- Vcs, ncsim, questa, or other simulator and associated waveform viewers such as verdi
- On-Chip Bus Interfaces and Architectures: AMBA AXI, OCP, PIPE
- Recent grads with exceptional academic record, related courses, and relevant research projects or prior co-op/internship experience, or
- Engineers with 1-3 years industry experience in Design Verification, or RTL Design with a strong foundation in Software Engineering
84
Senior Asic / Layout Design Engineer Resume Examples & Samples
- MS/PhD in EE/CS with 2+ years of hardware verification experience
- Hands on experience with design flows and methodologies used for chip verification
- Superior communication skills
- LI-AP1
85
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Good knowledge of design verification methodology, such as UVM or OVM
- Many experiences with simulation model creation and the testbench build
- Strong RTL coding with Verilog and familiar with front-end design flow
- Strong C/C++ software development experiences
- Be familiar with scripting language, such as Perl, C shell, Makefile
86
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Specification of key functional blocks of the chip set
- Design and implement the functional blocks using Verilog
- Working with the design verification team to define test cases and debug test cases in a multi-level test environment
- FPGA emulation for the design
- Define constraints for synthesis and static timing analysis tools
- Validation of the Silicon
87
Asic / Layout Design Engineer Resume Examples & Samples
- > Bachelors Electrical Engineering, Computer Engineering, or Computer Science
- > 5 years closely related experience
- > Demonstrate excellent performance history from current and/or previous employer
- > Strongly prefer GPGPU and/or 3D Graphics hardware experience
- Knowledge and experience can be gained concurrently or as part of an education curriculum
- System level RTL (hardware) bug hunter
- Using state of the art techniques, you will be responsible for verification at the functional model, and RTL level for graphics processing systems or sub-blocks
- Understand new compute or 3D graphics feature definitions and requirements; impact on the legacy, existing, and future product architecture, design and test case implications
- Identify the appropriate verification methodology, design the test plan, innovate and create the tests, debugging issues with the tests and/or hardware design being tested
- Collaborate with architects to understand features
- Create random graphics core level verification tests
- Review functional and code coverage metrics for the graphics core level - modify or add tests to meet coverage requirements
- Debug test failures to determine whether it is a design, environment or verification issue; work with the design team to correct defects and test issues
- Multiple projects authoring C/C++ code
- Understanding of system level requirements analysis
- Functional modeling in Software for hardware architecture
- Functional verification and debugging
- Proficiency in Verilog, System Verilog, UVM, Perl, Unix shell scripting, makefiles and the make utility, and working in Linux and Windows environments
- English language listening, speaking, reading, and writing capabilities
- Excellent communication and interpersonal skills both verbal and written for interaction with a large team across multiple sites
- Teamwork and interpersonal skills
- 3D Graphics Pipeline
- GPGPU Programming
- LINUX
- Makefiles
- Verification Methodologies such as OVM/UVM
88
Asic / Layout Design Engineer Resume Examples & Samples
- Develops software tools to automate performance and power analysis, modeling and tracking process
- Delivers useful 3D graphics performance resources to help identify potential performance bottlenecks in current and future benchmark applications
- Performs various in-depth performance/power analysis for current and future desktop, mobile and workstation products
- Constantly looking for better ways to enhance the current automation infrastructure to better support hardware and software graphics performance tuning
- Other tasks may include developing internal synthetic benchmarks
89
Pmts Asic / Layout Design Engineer Resume Examples & Samples
- Define micro-architecture, design and implement graphics features using Verilog, System Verilog, or C/C++
- Experience with high performance with low power design techniques
- Feature documentation and review preparation
- Test creation, verification, and debugging of graphics features
90
Pmts Asic / Layout Design Engineer Resume Examples & Samples
- Co-Work with Design Team and Performance Verification Team
- Lead Game Bottleneck Based Performance Verification, Evaluation and Analysis for new chip
- In pre-silicon
- Master with 8+ years or Bachelor with 7+ years of industrial experience of GPU or CPU
- Minimum of 5 years of experiences on hardware performance/function analysis
- Plus with experience on Compiler
- Plus with 3+ years’ OpenGL/D3D programming experience
- Familiar with Graphics Algorithm/Graphics Pipeline
- Good communication & Team worker
91
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Major in EE, CS or related
- Master with 2+ years or Bachelor with 4+ years experiences
- Familiar with Linux Environment
- Experience/Background on Computing/Graphics is a plus
- Experience with OpenGL/OpenCL/D3D programming is a plus
- Good communication and cross-site team work is desired
- Strong problem solving skill is desired
- Passion to work efficient and improve the current methodology
92
Senior Asic / Layout Design Engineer Resume Examples & Samples
- Master with 1+ years or Bachelor with 3+ years experiences
- Good at one of script language(perl, python, ruby, …)
- Good at C/C++/Verilog/SystemVerilog
93
Senior Asic / Layout Design Engineer Resume Examples & Samples
- > Masters in Electrical Engineering, Computer Engineering, or Computer Science
- > Will consider Bachelors Electrical Engineering, Computer Engineering, or Computer Science and 5 years closely related experience
- > Specialization in Hardware Functional Design Verification will get priority attention
- Identify the appropriate verification methodology, design the test plan, innovate and create the tests
- Strongly prefer GPGPU and/or 3D Graphics hardware experience
- Good knowledge of Software Engineering and excellent programming skills
- ASIC design knowledge and ability to debug Verilog RTL code using simulation tools
- Strong analytical thinking and problem solving skills with an excellent attention to detail
- Leadership experience preferred
- ASIC verification
- WINDOWS
- PERL or similar scripting language in UNIX or LINUX
- Verilog Hardware Description Language (HDL); Debug Verilog RTL code using simulation tools
- Synopsys: VCS Functional Verification, Verdi Automated Debug System
