ASIC / Layout Design Engineer Cover Letter

I would like to submit my application for the ASIC / layout design engineer opening. Please accept this letter and the attached resume.

In the previous role, I was responsible for quality assurance support and oversight for product design and development activities including: Design and Development Planning, Design Input, Design Output, Design Review, Design Verification and Validation, Design Transfer, Design Changes.

Please consider my experience and qualifications for this position:

• Experienced in STA and technique for timing closure
• Should be able to provide Technical mentoring and guidance to junior engineers
• Debug function/performance bugs of graphics chips
• Hand-on experience in all domains of complex ASIC DV flow from plan to coverage
• Good knowledge on verification methodologies like UVM
• Self-checking, reusable, automated verification environment
• Developing and maintaining models for various Server, APU and dGPU IPs
• Working with architects and project leads on verification requirements, metrics and platforms (IP, FPGA, emulation)

In response to your job posting for ASIC / layout design engineer, I am including this letter and my resume for your review.

In the previous role, I was responsible for guidance on New Product Development projects for: User Need Specification, Design Specification, Design Verification, Design Validation, Test Method Validation, Risk Management File, Design Transfer and Design Reviews.

My experience is an excellent fit for the list of requirements in this job:

• Good oral English and communication skill
• Excellent knowledge of verilog and a scripting language
• Knowledge of at least one EDA place & route tool (Cadence Innovus, Synopsys IC Compiler II, Mentor Olympus, ATopTech Aprisa)
• Hands on experience in large scale ASIC chip SOC verification
• Knowledgeable in all aspects of large complex SOC verification and validation of ASIC design flow
• Proven experience with the latest design verification methodology such as assertion coverage based driven verification (code & functional coverage), constraint random test generation, and familiar with the latest languages such as SystemVerilog, UVM/OVM, SystemC/C++
• Experience with Unix/Linux environment and good at scripts
• Experienced in ASIC design flows (RTL design, simulation, synthesis, static timing analysis, equivalence checking, multi-synchronous designs, IP/SOC signoff)

In response to your job posting for ASIC / layout design engineer, I am including this letter and my resume for your review.

Previously, I was responsible for quality leadership to new product development teams in the areas of design control, design verification and validation, design transfer, risk management, and specification development.

Please consider my qualifications and experience:

• Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification
• Good knowledge of systemverilog and UVM verification
• Familiar with linux environment, skillful at script languages like perl, ruby, C shell, Makefile
• Should be able to work closely with RTL Designers and teams across multiple sites
• RTL(verilog) coding and style checking
• Scripts based on makefile, perl, TCL or csh/tcsh
• Clock-domain-cross checking
• Logic synthesis or physical Synthesis

I am excited to be applying for the position of ASIC / layout design engineer. Please accept this letter and the attached resume as my interest in this position.

In the previous role, I was responsible for guidance for product development under Design Control e.g.: Market/User requirements, Functional Specification, Design Verification, Design Validation, Test Method Validation, Risk Management, and Design Reviews.

Please consider my qualifications and experience:

• Logic equivalency checking
• ECO(engineering change order)
• Top level integration, floor planning, pad-ring design
• Clock distribution
• Design for test, design for debug or design for power
• Experience with UVM and Perl is preferred
• Knowledge and experience of 3d pipleline graphics and compute engine
• Experience with D3D, OGL, OCL, etc a bonusStrong analytical thinking skills and excellent attention to detail

I would like to submit my application for the ASIC / layout design engineer opening. Please accept this letter and the attached resume.

In the previous role, I was responsible for functional design inputs into design documentation and formal/informal design reviews, including workflow definition, architecture design and mock-up development and human interaction implementation recommendations.

Please consider my qualifications and experience:

• Working knowledge of Design verification flows (test planning, constrained random testing, coverage closure, UVM)
• Experience in silicon bring up, lab debug and silicon qualification
• Working knowledge of Verilog, System Verilog, UVM, C/C++, Perl/Python
• Understanding of Computer Architecture, PCIE, Hyper-Transport, IOMMU, SMMU, AXI, HSA and PCI industry standards preferred
• Proven track record of managing successful silicon implementation consistently on schedule
• Knowledge of UVM and OVM verification methodologies
• Familiar with DC/ICC/PT/Encounter/RedHawk/Calibre
• Familair with back-end implemenation