Design Verification Engineer Resume Samples

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H Feest

Haven

Feest

85711 Golden Shoal

Detroit

+1 (555) 398 4177

85711 Golden Shoal

Detroit

Phone

p +1 (555) 398 4177

Experience Experience

Detroit, MI

Design Verification Engineer

Detroit, MI

Mueller and Sons

Detroit, MI

Design Verification Engineer

6) Flexible in working hours to accommodate working with co-workers in different time-zones
Working with architects and designers to develop technical specifications
Analyse results and provide recommendations to Product Engineering teams in order to improve product quality or to meet design intent
Execute the verification test plan by developing checkers, stimulus and coverage using System Verilog and/or C++ and running simulations
Team and personal development – You take time to drive your own development, whilst also encouraging team members and partners to do the same
Efficiently execute test plans on multiple platforms, measure progress and metrics, and work with cross-functional teams to achieve these results
Work closely with architecture and RTL designers to develop comprehensive verification plan based on IP core standard specification

Boston, MA

Digital Design & Verification Engineer

Boston, MA

Williamson and Sons

Boston, MA

Digital Design & Verification Engineer

Execute formal and functional verification, synthesisand static timing analysis
Execute power aware verification
Verification plan development, RTL/gate simulations to meet project target in both quality and schedule
Create and maintain verification plans
Proficient in English: speaking, reading and writing
Problem solving in case issue and bug found
Debug RTL and gate level simulations

present

Los Angeles, CA

Senior Ic-design Verification Engineer

Los Angeles, CA

Gulgowski-Schumm

present

Los Angeles, CA

Senior Ic-design Verification Engineer

present

Infrastructure work including developing scripts and tools for efficiency and quality improvements
Develop advanced verification environment and test bench components in System Verilog using VMM or UVM methodology
Networking domain knowledge (e.g. Ethernet, GFP, OTN)
Perform RTL code coverage, assertion coverage, and gate level simulations
Drive and adopt new verification methodologies and flows for efficiency improvements
Develop comprehensive test plan and implement test cases
Architect and develop verification environment and testbench components such as BFMs and checkers

Education Education

Bachelor’s Degree in Electrical Engineering

San Diego State University

Bachelor’s Degree in Electrical Engineering

Skills Skills

Excellent debug skills with ability to quickly and accurately root cause failures and make high quality verification fixes
Proficient in Solidworks
Ability to oversee testing and produce final reports
Excellent verbal and written skills
Excellent testing and "hands on" development aptitude
Electronics knowledge
Knowledge of optical communications
Good written and oral communication skills
Good communication and teamwork skills
Good communication skills and a team player

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15 Design Verification Engineer resume templates

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Senior IP Design & Verification Engineer Resume Examples & Samples

Detailed experience in digital front end design - including logic architecture and design, synthesis and timing analysis, plus experience using industry standard EDA tools
Detailed experience in verifying complex SoC, ICs and IPs- including test plan and test development and debug, constrained-random verification, with experience using Verilog/System Verilog/Specman/e / OVM/UVM
Bachelor of Science or equivalent degree in Electronics, Electronic Engineering or Computer Engineering
Minimum of 8 years experience in SoC. IC or IP digital design and verification
Strong logic design and verification skills
Excellent communication and team working skills

SOC Logic Design & Verification Engineer Resume Examples & Samples

Digital design (including RTL, preferably with Verilog)
Object oriented programming skills with C/C++ and/or SystemVerilog
UVM/OVM experience

Vlsi Design Verification Engineer Resume Examples & Samples

Strong communication and teamwork skills
Leadership experience at university and/or participation in extracurricular activities in student organizations and and/or community service
Prior internship experience
Coursework in C or C++ in a UNIX environment
Coursework in object oriented design
Introductory understanding of design verification principles and practices
Course work in computer architecture, software engineering, data structures, VLSI design, and fault tolerant computing
Solid understanding of basic EE fundamentals

Senior Vlsi Design Verification Engineer Resume Examples & Samples

BS, MS or PhD degree in EE, CE or equivalent
EE fundamentals, digital logic, and computer architecture
7+ years of experience in programming, data structures, software engineering, and Object Oriented Design (C++, JAVA, or other)
Strong commitment, self-motivation, communication, and teamwork skills
BS, MS or PhD degree in EE, ECE, CE or equivalent
EE fundamentals, digital logic design, and computer architecture
Experience in programming (C, C++, or JAVA)
7+ years of experience in RTL design

Asic Design Verification Engineer Resume Examples & Samples

Plan and execute the verification of complex digital design blocks by fully understanding the design specifications and interacting with design engineers to identify important verification scenarios
Identify and write all types of coverage measures for stimulus
Debug tests with design engineers to deliver functionally correct design blocks
Identifying verification holes and show progress towards tape-out
Experience with verification methodology such as UVM/OVM
Experience with the full verification life cycle
Strong scripting skills (Python, Perl, etc.)
The ability to quickly react and adapt to changes based on new requirements
Ability to be highly organized and self-motivated
“How do I break this?” mindset
Experience with formal verification and/or SVA
Specman
Bachelor's degree in Electrical Engineering and/or Computer Engineering and/or Computer Science

Design Verification Engineer Resume Examples & Samples

Ownership of a piece of our test bench(block or featues or methodology improvement),
Planning & execution of Verif testplans for UMC changes,
Bug fixes,
Debug of regression signatures and
Integration and re-use continious improvements towards Verif IP Xct standards
MS + experience in Verification
Experience or exposure to Verilog, System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement
Experience with OVM/UVM is highly desired
Experience with encryption/decryption of AES128-LRW desirable
Experience with memory controllers, memory models(ddr4, lpddr3, lpddr4, G5/G6,TSV, and/or HBM) and/or ddr phys is a plus

Senior Hardware Design Verification Engineer Personal Devices Resume Examples & Samples

Responsible for the design verification and qualification of consumer electronics products (hardware, firmware and software)
Help lead test strategy discussions, develop comprehensive test methodologies, plans & test cases to ensure all performance metrics meet product architecture/design requirements
Execute test procedures and debug proof of concepts or early engineering units
Provide leadership and direction to other Design Verification Engineers and Technicians and ensure the execution of testing and test plans are completed to the highest level of quality
Provide critical analysis and completed summaries of test data and performance metrics driving the right solutions, design changes, and bug fixes that meet the customer experience goals
Develop innovative test methods to ensure robust product qualification with fixtures and tools for automation, stress testing, performance, design margin and corner case variations
Provide critical performance data and use statistical data analysis techniques to set product test requirements and limits
Minimum BS in Electrical Engineering, Computer Engineering or similar field. MS preferred
6-12 years' experience with design and verification testing of consumer electronics hardware and firmware at component, sub-system and system level
Experience with the full product life-cycle (Concept, Specification, Design, Verification, Manufacturing & Sustaining)
Knowledge of device architectures & performance metrics for consumer electronics devices
Demonstrated ability to create comprehensive test strategies and plans based on design specs
Experience in hardware bring-up, characterization and failure analysis
Ability to develop test plans, procedures, and reports with concise summaries, graphs or charts
Experience developing complex test systems and automation using common test equipment
Ability to organize, analyze, summarize and present large sets of test result data
Project management skills plan and own assigned test areas, deliverables and schedules
Strong communication skills to clearly express technical concepts in verbal and written forms
Aptitude to plan work and execute efficiently while adapting as necessary in a rapidly evolving environment with minimal direction with strong organization
Able to work closely with Electrical, Industrial, Hardware, Software, Component, Reliability, Manufacturing and Compliance Engineers as well as Program Managers
Experience with high volume manufacturing, reliability, mechanical engineering, or end user system level product testing
Enthusiastic, motivated, self-driven, and reliable with strong work ethics and interpersonal skills
Experience with accelerated and environmental testing
Experience with statistical analysis techniques and DOE (Design of Experiments)
Experience running CAD tools for Circuit Simulation for design, modeling and analysis
Domestic and International travel may be required

Design Verification Engineer Resume Examples & Samples

1- Conferring with RTL Designers and SOC DV Leads on Verification Requirements and Strategies
2- Writing/Implementing/Reviewing Test Plans and Strategy Documents
3- Developing Verification Components for Re-Usable Verification IP in SystemVerilog
4- Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries
5- Analyzing Functional, Code, and Test Plan Coverage
6- Implementing Assertions, Checkers, and Monitors
7- Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools for Design Verification
8- Deploying Industry-Leading Verification Methodologies such as UVM
9- Triaging and Debugging Regressions
10- Replicating In-Silicon Bugs with Directed Simulations
11- Conducting and participating in Code Reviews
1- Creative and innovator and thinker who loves technical problems and detail-oriented tasks
2- Exhibits relentless commitment to help the team meet quality and development goals on schedule
5- Communicates openly and clearly in meetings, presentations, emails, and reports
6- Flexible in working hours to accommodate working with co-workers in different time-zones
Digital Design in RTL, Verilog HDL, SystemVerilog, OVM/UVM/VMM
C/C++, Java or other object-oriented programming language
Perl, Ruby, Shell-scripting, UNIX/LINUX Environment
PC System Architecture: PCI Express, HyperTransport, x86, ARM
I/O Virtualization (IOMMU, SMMU)
AMD Heterogeneous System Architecture (HSA)
Engineers with 2-5 years industry experience in Design Verification, or RTL Design with a strong foundation in Software Engineering

Design Verification Engineer Resume Examples & Samples

Be capable of defining and executing thermal component and thermal system-level tests to help validate system specifications
Minimum BSEE/BSCE with 3-5 years of experience
Experience in thermal design, measurements and analysis
Ability to debug system failures both HW and SW for root cause analysis

Design Verification Engineer Resume Examples & Samples

Working with architects and designers to develop technical specifications
Writing design verification specifications
Achieving excellent code coverage
Emulating RTL with models on FPGA-based systems
Verifying ECOs
Working with other leads to develop practical project schedules
LI-MG

Design Verification Engineer Resume Examples & Samples

4+ years user research experience in HW or SW products in a fast paced environment
Prior similar Beta program management experience
User research degree in Human factors or equivalent
Excellent interpersonal, communication (written and oral) and collaboration skills
Experience with team building, collaboration, and influencing others
Self-motivated, and results driven
Demonstrated experience working as part of a team to solve technical challenges

Design Verification Engineer Resume Examples & Samples

Participate as a development team member and work closely with design, marketing and user experience teams
Develop new test architectures and comprehensive test plans
Identify product risk areas and mitigate them through characterization and analysis
Be the customer advocate and translate customer use scenarios into measurable system performance attributes and test parameters
Use statistical data analysis techniques to identify critical performance metrics and limits
Interface with the Manufacturing Test team and provide critical to quality parameters and limits
He/she will be expected to lead technical teams consisting primarily of verification engineers in order to meet verification, validation and test deliverables
Manage external vendors and resources
5 years or more experience in design and/or verification of hardware devices

Design Verification Engineer Resume Examples & Samples

Work in a team of design verification and design engineers, involved in all aspects of the verification flow from initial test planning to coverage and signoff closure under aggressive, market-driven schedules
Build testbench components such as test libraries, models, monitors, scoreboards, sequencers, sequences, and BFMs by applying objected oriented design techniques and using advanced verification languages such as System Verilog, UVM and C++
Drive closure of regression signatures using waveform viewer and output files; and collaborate with RTL designers to fix bugs
5+ years of experience - Requires demonstrated technical expertise in functional verification of complex designs including: test planning, IP test bench development, stimulus generation, checking, and functional coverage
Significant experience with Verilog, System Verilog, and Object-Oriented Programming expertise are a requirement
Experience with UVM and Perl is highly recommended - Requires strong Programming and debug skills
Requires strong communication skills and the ability to work independently as well as in a cross-site team environment. The Graphics Memory Hub (GMHUB) is an IP that delivers into many SOCs that are shipped by AMD. We deliver console, discrete graphics, and low power SoC’s and use the same testbench to verify all of our IP. There are many challenges as we refine our new testbench and take on the next generation GMHUB architecture changes and challenges. This position will enhance or develop skills sets in all of the following: Verification methodology, OVM/UVM, Random Constrained Stimulus, Coverage Driven Verification and more

MTS Design Verification Engineer Resume Examples & Samples

BS degree in Electronics or Computer Engineering with 5 to 7 years of experience or BS + MS degree with 3 to 5 years of experience
Strong background in ASIC Design flow and Design Verification
Experience verifying designs using UVM, OVM or VMM
Familiarity with industry standard high-speed protocols such as PCIe, Ethernet, SATA and USB is a plus
Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality

Asic Design Verification Engineer Resume Examples & Samples

A truly multidisciplinary function, working in close collaboration with the front end designers and physical designers on the various SOC verification efforts
Interacting with a wide variety of internal and external design verification development teams, DV methodology, and Silicon IP and tool vendors
Work with architects, and the design and DV team to define develop Testplan and execute system verification plan from power management, system features e.g. power management, DFT DV, interoperability, multi-engine Security, Coherency, etc

Design Verification Engineer Resume Examples & Samples

Lead a high performance verification team
Architect and Implement leading edge verification solutions
Work closely with team members to understand the high speed CPU data fabric architecture and develop verification plans and tests to verify complex features of the chip
Execute the verification test plan by developing checkers, stimulus and coverage using System Verilog and/or C++ and running simulations
Design & develop productivity through process/tool/methodology solutions and take steps towards reusable and maintainable code that can be used over multiple generations of CPU/GPU products
Predict the scope of work and coordinate with all team across functional groups to set direction and establish priorities
At least 10 years of proven verification experience of complex CPU/ASIC projects
Proven technical leadership and mentoring skills
Experience with process and methodology improvements

Design Verification Engineer Resume Examples & Samples

1) Conferring with RTL Designers and SOC DV Leads on Verification Requirements and Strategies
2) Writing/Implementing Test Plans and Strategy Documents
3) Developing Verification Components for Re-Usable Verification IP
4) Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog/UVM
5) Analyzing Functional, Code, and Test Plan Coverage
6) Implementing Assertions, Checkers, and Monitors
7) Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools for Design Verification
8) Deploying Industry-Leading Verification Methodologies such as UVM
9) Triaging and Debugging Regressions
10) Replicating In-Silicon Bugs with Directed Simulations
11) And More…
2) Exhibits relentless commitment to help the team meet quality and development milestones
3) Drives to learn and perform at his or her highest potential in a technical capacity
4) Thrives in both a team environment and in individual contribution
5) Communicates openly and clearly in meetings, presentations, emails, and reports
6) Flexible in working hours to accommodate working with co-workers in different time-zones
Object-Oriented Programming
Verilog HDL, SystemVerilog, OVM/UVM/VMM
UNIX/LINUX Environment, Shell-scripting, Perl
Simulators: vcs, ncsim, questa, or other simulation tool
PC System Architecture: PCI Express, HyperTransport, ARM
On-Chip Bus Interfaces and Architectures: AMBA AXI
0 to 2 years equivalent industry or research experience, recent grads with co-op/internship in a related field preferred

Design Verification Engineer Resume Examples & Samples

MS in computer science, electrical engineering, mechanical engineering or equivalent experience required. PhD or advanced degree in Datacenter research strongly preferred
Demonstrated experience designing and executing experiments and research at the interface between datacenter and server engineering
Expertise in thermal dynamics and engineering methods including computational fluid dynamics simulation
Demonstrates ability to write, speak, and present information effectively and persuasively
Demonstrates critical thinking, precision questioning and problem solving skills
Self-starter who identifies opportunities and engages with limited management direction
Experience using MS Outlook, Word, PowerPoint, MS Project, Visio, and Excel. CFD and/or Reliability simulation software experience preferred

Asic Design / Verification Engineer Resume Examples & Samples

Design new clocks modules inorder to support high frequency clock with all the above constraints
Verify clock design with the industry standard tools to deliver high quality clock modules
Ability to design novel techniques to distribute clocks over long distances with low insertion delay, skew and OCV effects
Perform STA on the designed clock modules

Asic Design / Verification Engineer Resume Examples & Samples

Micro-architecture definition for system-level modules (fuse, strap, in-silicon measurement, etc�)
RTL design, synthesis, timing and silicon bring-up
Unit-level and system-level verification
Chip level integration

Functional Design Verification Engineer Resume Examples & Samples

MS + 5 yrs or BS + 9 yrs of Functional Verification experience
Requires demonstrated technical expertise in functional verification of complex designs including: test planning, test bench development, stimulus generation, checking, and functional coverage
Requires strong programming and debug skills
Significant experience with Verilog and System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement
Experience with OVM or UVM is a must
Experience with memory controllers, memory models(ddr4, lpddr4), Jedec and/or ddr phys is a plus
Requires strong communication skills and the ability to work independently as well as in a cross-site team environment

Senior Audio Design Verification Engineer Resume Examples & Samples

Theoretical and practical knowledge of psycho-acoustics and speech quality metrics
Experience with high volume manufacturing testing of the audio subsystem
Experience with Skype Certification
Experience with audio test SW such as AQUA and Artemis
Knowledge of Windows operating systems
Knowledge of Microsoft Word, PowerPoint and Excel

SOC Design Verification Engineer Resume Examples & Samples

MS/PhD in EE/CS
Hardware verification experience /internship is a plus
Hands on experience with design flows and methodologies used for chip verification is a plus
Superior communication skill

Pmts SOC Design Verification Engineer Resume Examples & Samples

Exposure to Power Aware verification
Working knowledge of languages such as C/C++/Verilog/SV/UVM/Perl etc
Working knowledge of emulators
Be able to work with functional teams across various geographies

Design Verification Engineer Resume Examples & Samples

Be responsible for the functional verification of a block(s) of IP cores for a state-of-the-art industry leading Data Fabric for AMD’s CPU/GPU SOCs
Be part of a team of verification engineers, working closely with other team members, designers and architects to understand and verify the functionality of a given design element within the context of the block, chip and overall system
Be responsible for carefully documenting and executing test plans consisting of directed and constrained-random tests to be run during simulation
Develop functional coverage and use feedback from code and functional coverage to enhance verification efforts
Minimum 7 years of proven verification experience of complex CPU/ASIC projects with demonstrated mastery of successful verification from test planning till tapeout
Proven developer of complex verification checkers and stimulus using SystemVerilog/UVM or equivalent for functional modeling of industry/internal interfaces
Experience writing and closing functional coverage on complex functions (substantial number of gates)
Development of reusable code used over multiple product generations

Smts Design Verification Engineer Resume Examples & Samples

Fully familiar with ASIC Design flow
Expert in Design Verification techniques and methodologies including UVM, OVM or VMM as well as Formality, Coverage-based Constrained-Random methodologies and Emulation
Proficient in Verilog, C++, System Verilog and Objected Oriented Programming in general
Strong analytical and problem solving skills with pronounced attention to detail

Pmts SOC Design Verification Engineer Resume Examples & Samples

BS/MS in EE or CS or CSE with 15 years of hardware verification and management experience
Minimum of 5 years of experience in managing engineering teams
Knowledge of SOC and system architecture
Working knowledge of languages such as C/C++/Verilog/SV/UVM etc
Be able to manage functional teams across various geographies
Ability to network, build relationships, and drive effective decision-making across multiple functions and levels within the organization and

Microsoft Hardware Design Verification Engineer Resume Examples & Samples

Be responsible for the complete end to end verification of our products
Participate in the development of our products from product inception to mass production
Sequence and prioritize product feature tests and ensures that there is adequate time for test coverage, trade-off decisions, and the timely completion of high-quality work
Works to meet platform and test milestones detailed in the project schedules. Identifies and escalates schedule risks, and offers solutions to stay on schedule
Develops, reviews, updates, and executes test plans for complex feature areas or products
Implements new data analysis tools and executes Measurement System Analysis (MSA) on Test and Metrology (T&M) equipment
Creates data collection templates to support test plans and increase data analysis efficiency
Uses statistical techniques to analyze test data against product requirements
Generates comprehensive test reports to communicate test results
Performs root cause analysis on verification test failures to influence product design changes to meet the product requirements
Identifies and escalates product risk areas based on test results and data analysis
Maintains and develops automated test tools and software
BS/MS in Mechanical Engineering, Electrical Engineering, Physics or similar field
2 years of hardware test experience
Hands on experience designing and fabricating test fixturing to support repeatable and automated verification tests
Experience scoping and implementing metrology equipment to support the development of new measurement methods
Proven LabVIEW programming capability for test tool maintenance and development
Excellent interpersonal skills including written and oral communications
Hands on experience with LCD display mechanical assemblies
Experience with flat panel display metrology, display optics, and display image defects
Mechanical design and CAD experience to support fixture design
Familiarity with robotics and automated machines a plus

HW Design Verification Engineer Resume Examples & Samples

Understanding of Bus Architectures (AXI or similar), Baseband/RFIC Interfaces, Network-on-Chip, various CPU/DSP Architectures, Multi-Domain Clocking and Power Management
Experience in developing and maintaining UPF Files for Power Analysis
Verification of Mixed-Signal IP's such as PLL's and LDO's
Understanding of Pre-Silicon Emulation for a Multi-Million Gate Count SoC
Experience with tools like Palladium/Zebu

SOC Design / Verification Engineer Resume Examples & Samples

Motivated, self-directed and able to work effectively both independently and in a team
BS or MS Degree in Electrical Engineering, Computer Engineering, or related degrees
Applicants must have a legal right to work in the US without sponsorship
At least 3 years of experience in Digital design (including RTL)
At least 3 years of experience in Verilog
Knowledge of SystemVerilog Testbench & Assertions

Design Verification Engineer Resume Examples & Samples

Develop and manage master verification plan on each design project dynamically in alignment with project schedule and deliver the design verification test plan/protocol/report timely
Lead regulatory compliance certification process, guide regulatory preliminary review on early design phase, provide inputs on design for regulation, support design improvement against regulation and connect to certification bodies/agents to complete certification
Develop reliability test plan with rational sample size and proper math models against failure-induced stresses
Develop test protocols, methodologies and proper testing fixtures and implement testing or tutor technicians to complete tests
Conduct test results analysis with statistic techniques and give independent judgment on design quality
Assure test data integrity, organized, traceable and documented
Assure the quality of the design outputs
Guide the design team to understand how to design tests to answer questions about the design, especially tests that don’t need to wait until the entire instrument is built
BS or higher in instrumentation, automation, biological engineering, electrical or electronic engineering, Electro-mechanical or similar
At least 5 years work experience in testing, verification & validation
Fundamental knowledge of statistical analysis techniques to assess whether design outputs have a statistically capable design and to identify special cause variation that should be investigated
Physical failure Knowledge to be capable to dig out failure mechanism and root cause
Knowledge of how to design and execute a life test, HALT/HASS and use statistical technique and math model to estimate new product lifetime
Fundamental skills to utilize statistics, reliability engineering and failure analysis on design verification practice
Experienced knowledge of electrical safety standards, EMC standards or related IEC or GB standards, environmental test standards and reliability engineering standards
Knowledge of DOE in designing good tests to answer questions
Good communication skills in Chinese and English
Strong quality sense to new product development
Passion for design verification and testing job
Willing to learn new products or new technologies
A proven quick learner and proactive self-starter
Open communication

Fuselage Design & Verification Engineer Resume Examples & Samples

Bachelor's degree from an accredited college in an engineering discipline with 7+ years of experience in Aircraft Structural Design
Experience with aircraft structural design
Experience mentoring and training engineers
Experience working on diverse engineering teams
Experience with military or government programs
US Citizen or legally authorized to work in US as a permanent resident. This position is located at a facility that requires special access
Ability to relocate internationally
Experience working with international customers
Experience with Export Control Compliance
Experience working in or with the Korean government or culture

CPU Design Verification Engineer Resume Examples & Samples

Design the verification architecture of a high-end 64 bit super scalar micro-processor
Draft and review the test scheme and test plan
Work with a team of DV engineers in development of all test cases, and test bench architecture
Coordinate the DV effort across multiple sites

Design Verification Engineer Resume Examples & Samples

This position requires a minimum of 7 years of experience in the verification of chip designs
Masters degree in EE is preferred. Experience in the development of wireless technologies is desired. -
Candidate should be familiar with some of the following; Verilog, VCS/NCsim, Questa, C-language or SystemC, Vera, Specman, System Verilog, VMM, UVM
Candidate must show a strong knowledge in the development of chip verification environments and a proven track record of taping out chips to production
Candidate focused expertise in CPUs, 802.11 WiFi MAC layer, high-speed peripheral interfaces (PCI-E/USB/SDIO), or any networking technology beyond verification knowledge is definitely a plus

Design Verification Engineer Resume Examples & Samples

Expertise in System Verilog or equivalent object oriented verification methodology
Experience in script writing in PERL, Python
Knowledge of C, C++ and UNIX
Experience in full chip verification techniques
Exposure to the various verification techniques such as coverage based verification, formal verification techniques etc
Experience in writing tests/testplans and test bench components for both functional blocks and full chip
Experience on standard bus protocols such as DDR2/3, PCI-E/SATA/USB/Ethernet etc

Design Verification Engineer MW Resume Examples & Samples

Perform verification planning and AMS simulation
Implement functional verification of mixed-signal ASICs
Develop testbenches
Failure analysis and resolution, coverage analysis and population
Digital/mixed-signal modelling
Develop directed/constraint-random test generation, gate-simulations
Regression debug support, and other flow/inftrastructure development
MS or PhD in Electrical Engineering or Computer Engineering and 5+ years of verification experience preferably in mixed signal products
Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/OVM, UVM, AVM, Vera)
Able to work closely with digital/analog designers, applications engineers, and manufacturing test to support both pre-silicon verification and post silicon validation efforts
Knowledge of signal processing and Verilog Assertions
Ability to create, evaluate, debug, and improve a verification process
Ability to mentor junior engineers in verification methodology

Entry Level Design Verification Engineer MW Resume Examples & Samples

Develop verification planning for mixed signal designs
Develop testbenches for mixed signal designs
Employ failure analysis techniques
Review coverage analysis and population
Develop digital/mixed-signal modeling
Use directed/constraint-random test generation and flow development
Requires a MSEE/MSCS and 5 years of verification experience preferably in mixed signal products
Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/OVM, UVM, AVM, Vera, e) required
Must have solid scripting skills with Matlab, Perl, Unix/Linux shell, TCL, and must be able to write and debug analog behavioral models in Verilog, Verilog-A, and/or Verilog-AMS
Knowledge of signal processing and Verilog Assertions are also a plus
The proven ability to create, evaluate, debug, and improve a verification process is preferred for this position

Intern Design Verification Engineer Resume Examples & Samples

Full-chip functional verification on Micron’s non-volatile memory design projects
TestBench Development in SystemVerilog targeting complete functionality coverage
Support of SystemVerilog assertion and coverage-driven methodology
Behavioral model development of Micron’s non-volatile memory
Support of design verification methodology enhancements
Able to work both independently and as part of cross-functional team

SOC Logic Design & Verification Engineer Resume Examples & Samples

3+ months of experience in computer architecture
3+ months of experience in Digital design (including RTL, preferably with Verilog)
3+ months of experience in Circuit design (understanding of clocking, basic circuits, timing issues)
3+ months of experience in Object oriented programming skills with C/C++ and/or SystemVerilog
3+ months of experience in SystemVerilog Testbench & Assertions
3+ months of experience in UVM/OVM

Physical Design Verification Engineer Resume Examples & Samples

Coding/supporting physical verification flows
Demonstrate experience working with UNIX, C++, python/tcl/Perl and Make
Mentor Calibre tool suite
Cadence Physical Verification System and SKILL programming language
Synopsys Hercules physical verification suite, PrimeYield tool suite

CPU Design Verification Engineer Resume Examples & Samples

The ideal candidate should have 5+ years of CPU verification experience
In-depth knowledge of digital logic design, chip architecture and microarchitecture
Experience with advanced verification techniques such as formal and assertions a plus

GPU Memory Hierarchy Design Verification Engineer Resume Examples & Samples

The ideal candidate will have relevant 3 plus years of experience including
Expertise with verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman experience is a plus
Strength in creating software solutions utilizing object oriented programming concepts
Experience defining coverage space, writing coverage model, analyzing results
Experience working under strict schedule deadlines with the ability to manage multiple priorities
Strong knowledge of computer architecture, general purpose microprocessor
Experience and expertise in memory/cache sub-system micro-architecture, which could include L1, L2, L3 caches, coherent interconnects, MMUs or related blocks
GPU experience, especially in the memory hierarchy area, is a plus

Design Verification Engineer Resume Examples & Samples

The ideal candidate will have 10+ years of wireless communications system experience in developing commercial wireless SOC products for very high volume mass production
▪Deep understanding of wireless protocols and network architecture
▪In depth experience with a standard wireless communication protocol such as 3GPP, 802.11 or Bluetooth. Must have prior experience deploying a wireless modem to the field and associated inter-operability issues
▪Deep familiarity with embedded CPU, bus architectures, security and modern embedded software development issues
▪Hands on experience with performance optimization and productization of high volume commercial wireless devices highly desirable
▪Experience with the system modeling and simulation of wireless networks

Formal Design Verification Engineer Resume Examples & Samples

Advanced knowledge of CPU or preferably GPU design architectures, VLSI circuits, and digital logic design
3 plus years of experience in formal verification and analysis of pipelined micro-architectures, MMU’s, and cache coherency control mechanisms
Strong experience with formal tools, such as Jasper, IFV, etc
Deep understanding of abstraction techniques and formal verification technologies
Knowledge and experience in reviewing and interpreting hardware specifications
Experience with HDL's such as Verilog/System Verilog and temporal logic assertion-based languages such as SVA
Hands-on experience in using EDA formal verification tools. Experience in using academic tools is a plus
Proficiency in programming/scripting languages with excellent debugging skills
Knowledge of constrained random verification methods is a plus

Design Verification Engineer Resume Examples & Samples

The ideal candidate will have at least 3+ years of relevant experience including
Expertise with Verilog and/or VHDL
Expertise with HDL simulators and waveform viewers like IES, VCS, DVE, Verdi
Strong knowledge of Computer Architecture; Graphics architecture is a strong plus
Experience with Perl, Shell scripting, Makefiles, TCL
Experience with linting tools; Spyglass is a strong plus
Experience with code repositories; Perforce is a strong plus
Experience with Formal Property Checking is a plus; Jasper is a strong plus
Experience with verification language such as SystemVerilog/UVM/OVM is a plus

Design Verification Engineer Resume Examples & Samples

Typically requires at least 6+ years of experience in design verification and an interest in power optimization
Familiarity with Verilog and System Verilog
Familiarity with script writing in Perl or Tcl
Familiarity with C, Assembly programming, and associated tool chains
Familiarity with verification environments, RTL design characteristics, simulation tools, and emulation tools
Knowledge of SOC power characteristics and intended usage for mobile products a plus
Ability to quickly understand and work with new tools
Good communication skills to work across multiple disciplines

Sensor Design Verification Engineer Resume Examples & Samples

1-3 years of related industry experience in a Design Verification and/or Product Engineering role (3+ years preferred)
Proficiency in scripting languages (such as Python/MATLAB), software development languages (such as C/C++), and statistical analysis software (such as JMP)
Background and experience in electrical and/or mechanical design of fixtures and/or robots
Excellent critical analysis, statistical analysis, and logic/reasoning skills
Excellent teamwork and leadership skills
Experience with sensor technology is a plus

Design Verification Engineer Resume Examples & Samples

The ideal candidate will be well rounded in all aspects of verification
Experience with low-level programming of complex computer systems in C/C++/assembly
Familiarity with verification environments, UVM, System Verilog is a plus
Knowledge of formal, hardware acceleration all plusses

SOC Design Verification Engineer Resume Examples & Samples

Advanced knowledge of CPU & SOC architecture/design & in-depth knowledge of verification flow
Familiarity with verification environments, UMM, System Verilog is a plus
Knowledge of industry standard interfaces, good understanding of Verilog, Verilog simulator and debug

Physical Design Verification Engineer Resume Examples & Samples

The ideal candidate will have 5-10 years of physical design experience, with emphasis on physical verification
Strong knowledge of physical verification flows and methodology
Knowledge of all aspects of ASIC physical design
Scripting skills to debug flow related issues and make enhancements as appropriate
Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc
Real chip tapeout experience with a track record of successful signoff
Layout design background and experience a plus

MMU Design Verification Engineer Resume Examples & Samples

The ideal candidate will have at least 5+ years of relevant experience including
Experience with cache verification and memory subsystem testing
Expertise in address translation concepts
Expertise with a verification language such as SystemVerilog/Vera/Specman/e
Experience with common verification methodologies such as UVM/OVM
Expertise with HDL simulators and waveform viewers
Strong fundamental software and programming skills
Graphics architecture and programming (OpenGL) highly desired

Memory Design Verification Engineer Resume Examples & Samples

The ideal candidate should have 2+ years of processor verification experience
In-depth knowledge of digital logic design, CPU, and cache architecture and microarchitecture
Strong programming (C/C++, Verilog, Scripting), Software optimization and performance enhancement skills
Experience in developing C-Based Xtors, unit and full chip level test bench
Knowledge of the CPU coherency and memory ordering
Experience in developing testplans, assertions, and writing/debugging assembly based tests
Experience with advanced verification techniques such as formal is a plus

Design Verification Engineer Resume Examples & Samples

The ideal candidate will have more than 3 years of direct verification experience
Advanced knowledge of chip architecture/design & in-depth knowledge of verification flow
Familiarity with verification environments, VMM, System Verilog is a plus

Design Verification Engineer Resume Examples & Samples

Experience in development of tests based on test-plans or functional specification
Experience with verification methodologies like OVM/UVM
Chip design experience using industry standard hardware description languages (Verilog/System Verilog) is required
Verification ofvprocessors and cache coherent memory systems would be an advantage
The candidate should possess knowledge of the state-of-art design-for-verification methodologies and have hands-on working experience in use of modern verification techniques, tools, and languages. Knowledge of SystemC or,C++/OOP and have a strong background in data structures and algorithms is desired
Experience in the following tools is desired: Formal Design Verification (Jasper, 0-in, IFV, OneSpin, SLEC, Model Checking); Low-Power Design Verification (UPF, CPF, Power Artist, AVS)
Scripting languages, preferably Perl, Python, Tcl, etc
Candidates must have at least 5 years of hands on experience using advanced verification methodologies and functional verification of advance SoCs
Formal and assertion based Verification experience is a plus. Some experience in design is preferred

Mst-asic-design / Verification Engineer Resume Examples & Samples

Verify design and debug in RTL-level, gate-level and PG gate level
Simulation, Design constraints, Coding Style checking, Cross clock domain checking, Synthesis and timing closure,
Work closely with verification/system/Firmware engineer to verify/validate new IP/product

SOC Design Verification Engineer Resume Examples & Samples

Strong critical thinking, problem solving and test planning skills
General knowledge in ASIC design process, digital design, design (hw/sw) verification tools and techniques, computer architecture, etc
Familiar with the design, verification and assertion languages: RTL, VHDL, Verilog, System Verilog, System Verilog Assertions (SVA), Vera, e-Specman, etc. –
Knowledge of SOC, ARM processor, AMBA bus, DDR, or peripherals is preferred -Scripting and automation skills: Unix/Linux shell programming, Perl, Makefile, revision management (e.g. CVS, ClearCase) is a plus
As verification is a rapidly changing field and consumes the majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do
Assertions, simulation, formal verification, HW-SW co-verification and constraint/HVL-based verification are all tools in our verification toolbox you will use on a daily basis

IC Design Verification Engineer, Sequencing Resume Examples & Samples

Ownership of all aspect of the design verification of the chip and/or its functional blocks and IP
Ownership of system, chip, and IP models for verification
Evaluation and selection of flows and EDA tools
Development and deployment of processes and flows for Design Verification
Test Plan ownership, and coordination with Architecture, Design, DFT, and other teams to deliver a complete, comprehensive verification plan

CPU / Processor Design Verification Engineer Resume Examples & Samples

Experience with expertise in developing testplans/testbenches, C-based transactors, and writing/debugging assembly based tests
Experience in silicon bringup a plus
Should be a team player with excellent communication skills, be able to work independently on the verification efforts for a block/area of the design

Design Verification Engineer Resume Examples & Samples

MS in Computer science, Electronics engineering, Math or related technical field
Class taken in C/C++
Class taken in or internship using Verilog/VHDL
Class taken in or internship using UVM or System Verilog

Design Verification Engineer Resume Examples & Samples

Experience in verification using random stimulus along with functional coverage and assertion-based verification methodology
Experience with UVM/VMM environment block level and system level verification
Knowledge of industry standard communication protocols
Debugging in debugging
BS in Electrical Engineering or equivalent with 5 years of verification experience

Design Verification Engineer Resume Examples & Samples

5 or more years of experience in a relevant field
2 or more years of experience coding and debugging in C, C++ and/or C#, and in the Windows Platform
2 or more ship cycles
4 or more years in Customer facing engineering solutions, consultant or equivalent role. Domestic and international travel may be required

Design Verification Engineer Resume Examples & Samples

Masters degree in EE is preferred. Experience in the development of wireless and/or Application Processors technologies is desired. -
Familiar with some of the following; Verilog, VCS/NCsim, Questa, C-language or SystemC, Vera, Specman, System Verilog, VMM, UVM
Expertise and in-depth knowledge of HW emulation, hardware and system validation

Pre-silicon Design Verification Engineer Resume Examples & Samples

6 plus years of pre-silicon design verification experience
Master’s degree or higher preferred
8 plus years of pre-silicon design verification experience preferred
Able to demonstrate innovative and analytical thinking
Able to plan and organize day to day activities and execute according to plan

DFT Design Verification Engineer Resume Examples & Samples

The ideal candidate will have relevant experience including
Experience with verification language such as SystemVerilog is a plus
Experience with Verilog is a plus
Knowledge of IEEE 1500/IEEE 1149
Experience with Verdi and debugging problems with waves
Experience with Perl, Shell scripting, Makefiles, TCL a plus
Excellent communication skills and ability to collaborate

Consultant Design Verification Engineer Resume Examples & Samples

Review Detailed Design specifications for logic to be tested
Work with IP vendors and Design engineers to resolve bugs
Expertise in ASIC or FPGA RTL design verification
Strong experience in software design, using classes
Ability to interface with other disciplines, including RTL/Logic, hardware design, and firmware engineers
BS, MS CS, EE or related discipline, or 7+ years of equivalent experience
History of solving technical problems, solo and in a team

Design Verification Engineer Resume Examples & Samples

Lead verification team and provide mentorship to junior members
Work closely with architecture and RTL designers to develop comprehensive verification plan based on IP core standard specification
Implement SystemVerilog/UVM based verification environments and ensure functional correctness of IP cores
Drive regression, functional coverage analysis and closure
Customer support by troubleshooting, testing and debugging issues related to IP and system
Requires at least 2+ years of industry experience
Experience in coverage driven verification using UVM/OVM
Strong understanding of Verification and Validation Principles with analytical mindset and problem-solving skill
Must be a team player with excellent communication skills in both written and verbal
Experience in High-Speed Serial IO protocols (Ethernet, CPRI etc) and transceiver is a strong plus

Digital Design Verification Engineer Years Contract Resume Examples & Samples

Pre-Silicon functional & power aware verification, formal verification desired
Defining and enhancing methodologies for pre-silicon verification of high speed and high complexity designs, and improving the overall efficiency and velocity of pre-silicon verification
Test bench development, test content development, cluster, DFX validation, Adapting Verification components and other aspects of pre-silicon verification
Setting up verification plan, defining and running system simulation model finding and implementing corrective measures for failing tests
Analysing and using results to modify testing- RTL design in VHDL and Verilog/SV
Close interaction with RTL designers, Analog/Mixed signal designers, product architecture, logic design, design automation, post-silicon validation and test development teams to ensure high quality design validation and product delivery
Test chip and product verification, test vector generation- Technical documentation
Strong scripting and tool setup skills

Senior Pre-silicon Design Verification Engineer Resume Examples & Samples

4 plus years of experience in ASIC design and pre-silicon validation
4 plus years of experience in SystemVerilog based OVM/UVM, VMM or related object oriented and coverage driven verification methodology
Master’s Degree or higher is preferred
8 plus years of experience in ASIC design and pre-silicon validation
2 plus years of experience in leading a team to develop and implement a large ASIC validation strategy
Experience in Java, C/C++ & logic design
Experience in perl, sh, and python
Experience with VCS and collecting coverage
Familiarity with continuous integration flows and xml
Understanding of PCIe, Ethernet and networking

Senior Nand Design & Verification Engineer Resume Examples & Samples

BS & 4+ years or MS & 3+ years in the following areas
Verilog / System Verilog design and verification
High level programming language such as C++, perl, tcl
Logic and or Mixed signal design and verification
Semiconductor Device Physics
CMOS circuit / analog circuit design and verification
NAND Flash or NOR Flash or Non
Volatile Memory Experience

Design Verification Engineer Resume Examples & Samples

Solid knowledge and experience of TestBench development in SystemVerilog
Experience in behavioral model development
Experience in scripting languages such as TCL and PERL

Design Verification Engineer Resume Examples & Samples

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1) Participating in the verification processe
2) Understanding the architecture and implementation of these chips and coming up with in-depth test plans for verifying various key features of chips and systems
3) Developing verification environments including test benches and verification associated with the chip architecture to enable testing of various features within the chips as well as scripts and Make files as required to run the environment in various tool chains
4) Implementing test plans into executable test suites using a cutting edge System Verilog verification environment as well as leveraging high performance verification platforms such as test bench acceleration and In-circuit emulation as required
5) Executing the verification process to completion pre-silicon using various functional and code coverage metrics as measures of completion

Msip-digital Design & Verification Engineer Resume Examples & Samples

Evaluate and deploy the most efficient designs techniques for delivering increasingly complex Mixed Signal Analog IP within aggressive, market-driven schedules
Ensure quality adherence during all stages of the project life cycle. Also carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure ‘Zero Defect’ designs
Own and Lead digital wrappers and controller design and verification through the concept till IP delivery and post Silicon debug support
Influencing and building technological innovations for self and in team environment
Self-starter with 4-12 years of experience on IP design and verification of Sub-system/SOC level multimillion Gate and complex Design with multiple clocks and power domains - with minimal supervision
Work on Design, Testbench, Testplan and Testability aspect of digital controller part of Analog Mixed signal IP along with functional requirements
Experience and extensive hands on knowledge of HVLs (UVM/SV/C++/SC/e/VERA), HDLs (Verilog/VHDL),PLI/DPI, simulators (NCSim/VCS/ModelSim)
Exposure to formal verification methodology, assertions/SVA, functional coverage, gate level simulations, verification planner and regression tools
Exposure of Analog IPs like ADCs, PLLs, internal and external Oscillators and Regulators
Experience in microcontroller architecture protocols like AHB/AMBA,AXI and memory controllers
Experience in Low power designs with various Clock gating, DVFS techniques
Scripting languages (Perl, Tcl), C/C++
Hands on work on pre silicon validation using FPGA/Palladium would be a significant added advantage

SoC Design & Verification Engineer Resume Examples & Samples

Digital logic design and/or verification
High-level verification language (System Verilog preferred)
Logic simulation tools such as Modelsim and VCS
5 years in a technical leadership position
Strong and proven technical leadership skills
Motivated and self-directed-Good planning skills

Senior Ic-design Verification Engineer Resume Examples & Samples

Develop thorough understanding of IEEE Ethernet protocols
Understand chip architecture, micro-architecture and design specification
Develop advanced verification environment and test bench components in System Verilog using VMM or UVM methodology
Verify some building blocks in a chip
Infrastructure work including developing scripts and tools for efficiency and quality improvements

IC Design Verification Engineer, Entry Level Resume Examples & Samples

Develop, execute and debug a wide range of functional tests in a verilog simulation environment for content processing hardware IP designs
Analyze requirements, assist in defining verification plans and strategy
Develop simulation testcases, including drivers and monitors
Work closely with IC Design Engineers
Determine RTL code coverage and address coverage issues
Assist in development of verification environment
A bachelor degree in Electrical Engineering or Computer Engineering program
Student work experience in hardware design or verification environment
Focus on quality of results, with proven problem-solving abilities
Ability to effectively communicate verbally and in writting in English and work within all levels of the organization
Must be a dynamic team player
Knowledge of digital design verification including test environment implementation and test plan development
Knowledge of C, object-oriented programming, System Verilog, UVM and/or other verification languages and simulators
L2 and L3 networking protocols implementation (e.g. Eth/IP/UDP)
Good knowledge of Unix/Linux, Perl, LSF

Design Verification Engineer Resume Examples & Samples

Experience in formal verification of hardware design
Experience in large scale logic design verification projects
Solid knowledge in System Verilog Assertion (SVA)
Must be willing to work weekends or evenings, if necessary

Senior Audio Design Verification Engineer Resume Examples & Samples

Experience with Hardware Verification Languages (HVL) such as SystemVerilog (UVM), Vera, SystemC, etc
Extensive experience with constrained random verification and assertion based verification methodologies
Experience with Low Power verification techniques
Knowledge of scripting languages such as Perl and/or Python
Good working experience with C and ARM assembly
Understanding of ASIC/VLSI concepts
Experience using RTL simulators such as Synopsys VCS, Mentor Graphics Questa and/or Cadence Incisive

Design Verification Engineer Resume Examples & Samples

Developing SystemVerilog UVM testbenches for block-level functional verification of units within the Coherent Mesh Network and Memory Controller
Creating and maintaining detailed verification plans
Generating and running testcases on logic simulation models
Debugging functional errors in the RTL model, using simulation tools, debug tools and based on in-depth understanding of the architecture and RTL design of the Coherent Mesh Network and Memory Controller
Defining and implementing functional coverage, and enhancing the testbench to ensure coverage closure
Promoting and demonstrating the ARM core beliefs and behaviors
Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (eg AMBA5 CHI, AMBA4 ACE or AXI)
A minimum of 5-10+ years of experience in pre-silicon verification
Experience in the specification, creation, and debug of SystemVerilog/UVM constrained-random testbenches
Experience with functional coverage driven verification methods
Good software engineering skills including understanding of object-oriented programming, data structures, and algorithms
Bachelors or Master’s degree in Computer Science or Electrical/Computer Engineering, with a GPA of 3.0 or higher

Senior Test Chip Design & Verification Engineer Resume Examples & Samples

6+ years relevant experience in the industry with good relevant degree
A thorough understanding and experience of the current verification strategies required for SoC development, including software based techniques
A good understanding of ARM System Architectures, ARM technology, culture and the business model
Low-level programming experience including C and Assembler
Expert knowledge of Verilog and SystemVerilog
UVM / OVM / e
Perl , Python or other scripting language
Ability to drive and document whole design process from engineering specification creation to fully validated RTL
Ability to plan and track validation for complex SoC’s
Experience of leading small teams and project planning
Excellent communication skills: listening, understanding and persuading
Highly self-motivated with the ability to effectively work alone as well as in a team
Hardware emulation / acceleration
Project management and leadership skills
Power aware verification
Clock domain crossing verification
Knowledge of Design For Test (DFT) and ATPG verification
Formal verification techniques
Tester vector creation and debug
Knowledge of backend implementation flows

Design Verification Engineer Resume Examples & Samples

SOC level Integration and functional verification of a complex CPU/GPU SOC
Work closely with a team members to understand and verify new and existing design features
Debug of Verilog RTL and System Verilog & C/C++ testbench at the SOC-level
One or more of the following
Measure performance metrics against specification
Integrate Verification IP and maintain working verification environment
Verify complex features include coherency and power related features
10 or more years of proven SOC level verification experience on large SOCs
Knowledgeable in C/C++, OO programming, Verilog, System Verilog, and scripting languages (Perl, etc)
Familiar with constrained random verification
Excellent debug skills, ability to analyze and isolate design/testbench issues using various techniques including waveforms and log files
Familiar with hardware modeling and/or assertion-based verification methods
Experience in one or more of the following areas
Measuring feature performance metrics against specification is required
SOC Level Verification IP integration
Data Coherency Feature Verification in complex data path SOCs
Power aware simulations which may include gate level verification of power aware features
Background in GPU/CPU architecture along with significant memory system and /or SoC architecture experience is important

Design Verification Engineer Resume Examples & Samples

Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification
Create testcase and testbench with UVM methodology
Fullchip/system functional verification, by define verification strategies/methodology and test plan to enable effective verification
Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
Experience on Emulation will be an add on
8+ years of experience with complex ASIC designs and/or verificationExperience in leading a small team of engineersFamiliar with System Verilog languageExperience on UVM verification methodology, and formal verification methodStrong communication skills and the ability to work with a team spread across different geography sitesFlexible in dynamic environment

Senior Digital IC Design & Verification Engineer Resume Examples & Samples

Be responsible for the digital RTL design(System Verilog, VHDL, Verilog)
Implementdesign-for-test concepts
Be the interface to the place & route colleagues
Create and maintain verification plans
Execute power aware verification
Debug RTL and gate level simulations
Do System Verilog modeling

Design Verification Engineer Intern Resume Examples & Samples

This team covers the product process from Design to manufacturing to ensure products are top quality and capable of being manufactured
0-1 years experience in Photography or Video production
Knowledge of editing processes and audio/video equipment and studio set-up (lighting, backdrops, green-screen, etc.)
C++/C# programming
Knowledge of mechanical control systems
Communications course work

Design Verification Engineer Resume Examples & Samples

Job Responsibilities
Actively involved in all stages of product development including specification, design, synthesis, verification, timing analysis, design for test and silicon debug
Develop and verify self-tested test benches for Mixed Signal chips and sub-circuits
Experience in Verilog RTL coding and versed in VerilogAMS, VerilogA, Verilog (or SV) languages
Proficient developing design constraints and Synthesis scripts
Experience with scan insertion and ATPG generation
Proven track record of released products
Must be able to work independently with limited supervision. Must be very organized, self-motivated and passionate about the work
PhD with 7+ years or MSEE with 10+ years (or BSEE with 12+ years) of relevant industry experience with a strong background in digital design. Exceptional talent may be credited towards education and experience requirements
Language skills: Written and verbal English language proficiency required
Tools: Cadence Design Tools and Synopsys DC proficiency required. Cadence AMS design flow experience is a definite plus

Design Verification Engineer Resume Examples & Samples

Candidates must be pursuing a Master’s degree or higher in Electrical Engineering
Strong understanding of transistor-level analog circuit design
Experience with electronic bench test equipment
Experience with Verilog RTL coding and verification concepts
Programming/scripting skills such as C, Perl, Python, etc
Knowledge of Matlab and Spice is a plus

Digital Design & Verification Engineer Resume Examples & Samples

Mixed-signal integration and verification involving DACs, ADCs, power supplies
Traditional and Object Oriented software development and debug in languages such as C, C++, C#, assembly, Perl, etc
Driving synthesis, APAR, timing analysis, and ATPG tools

Design Verification Engineer Resume Examples & Samples

Experience with Mixed Signal verification
Experience with Assertions & Coverage for Analog/Mixed-Signal
Modeling of analog (Real Number Models)
Formal Verification
Experience with Cadence based Verification tools: IUS, ePlanner, eManager, IFV, Conformal
TLM, Virtual prototype
Experience working with off-shore flex resources

Design Verification Engineer Resume Examples & Samples

Verification of audio silicon systems in an advanced UVM/SV environment
Leading metrics driven verification of complex systems
Working with design and verification teams to quickly debug silicon issues
Driving improvements in methodology to achieve greater quality of verification
Verification of DSP systems, including frequency domain and FFT analysis
Verification via System Verilog Assertions

Principal Design & Verification Engineer Resume Examples & Samples

Experience at system level and successful track record of designing and verifying complex SoCs through the whole lifecycle
Great communicator with customers and internal and external stakeholders
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product
Experience of system level and block level RTL design and verification for non-trivial FPGA/ASIC developments
Experience of development of coverage-driven constrained random test environments
Technically Managing a team of engineers on your assign project
Designing, implementing and verifying high performance, low power parts of IoT System and IP in Verilog RTL
Ability to work as part of a global team
Collaboration and communication
Creativity and innovation
Impact and influence

Design Verification Engineer Specialist Resume Examples & Samples

Plan, implement, test, document and maintain solutions for the integration and test of multiple projects
Review, evaluate, and derive requirements for testability
Develop verification test plans for safety-critical and high-reliability systems
Coordinate associated procedures and schedules with project teams
Perform independent verification and generate formal test reports
Execute verification efforts within technical, schedule, and cost constraints
Track bugs and technical problems and work with the design team to ensure timely resolution
Degree in Electronics, Electrical, Computer, Systems Engineering, Computer Science or Equivalent
Experience testing or developing software, VHDL or systems
Desire to work primarily on verification activities for new designs
Process-oriented mindset
Experience developing with OOP
Experience developing VHDL
Hands on experience with functional testing, debugging and lab equipment (logic analyzers, oscilloscopes, etc)
Experience writing test plans or procedures
Experience working with Requirements Management tools such as DOORS

Lead Design Verification Engineer Resume Examples & Samples

Main focus for this position will be Emulation
Port databases to Emulation environment
Execute workloads, and then debug them on the Emulator
Develop UVM Test-benches
Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure completion
Build a constrained random environment for various functional blocks as well as for full chip testing
Develop tests and tune the environment to achieve coverage goals
Debug failures and work with logic designers to resolve issues
Demonstrate good analysis and problem-solving skills
Must be diligent and detail-oriented
Willing to take initiative and handle assignments with minimal supervision
Must be self-driven and a good team player

Digital Design & Verification Engineer Resume Examples & Samples

Involving in concept definition and RTL coding
Define verification objects according to specifications and system requirements
Test environment setup, maintenance and optimizations
Verification plan development, RTL/gate simulations to meet project target in both quality and schedule
Problem solving in case issue and bug found
Master or Bachelor degree majoring in EE, with 6+ years related experience
Proficient digital design experience with VHDL/Verilog
Skillful in with simulation tool: Questasim, VCS
Software languages: C/C++, Perl, TCK, UVM is strong plus
Excellent problem-solving skill and a fast learner
Proficient in English: speaking, reading and writing

Principal Design Verification Engineer Resume Examples & Samples

Work experience in SoC verification using System Verilog, SystemC or UVM: 7+ years with MSEE or 10+ years with BSEE
Expertise in developing block level / system level verification environments
Expertise to develop BFMs / checkers / monitors / scoreboards
Experience in developing block/system level verification plans and tests
Must have capability to debug test failures to find the root cause both at RTL and gate level. Able to resolve complex timing issues found during back-annotated gate simulation
Experience in code / functional coverage
Experience in constrained random testing
Knowledge of scripting languages like Perl and Unix Shell language
Tools : Experienced with Synopsys, Cadence and Mentor design and verification products

Pre-silicon Design Verification Engineer Resume Examples & Samples

6 plus years of pre-silicon verification experience
6 plus years of experience and understanding of functional verification fundamentals encompassing state machine verification, complex protocol verification, functional test strategies, directed and stress test generation, verification infrastructures and verification and/or debug flows
4 plus years of experience in programming and/or scripting C++, Perl, Python or others and be conversant with flows and tools for VLSI logic design and/or functional verification
Knowledge on Computer Networks is a plus
6 plus years of experience and knowledge of System Verilog and working knowledge of verification methodologies like OVM and UVM
4 plus years of experience and knowledge on functional and code coverage

Entry Level Design Verification Engineer Resume Examples & Samples

Bachelors', Master's or PhD in Electrical Engineering or Computer Engineering
Proficiency with C/C++ programming, scripting such as Python, Verilog, System Verilog, UVM, and development best practices
Experience building testbenches and verification infrastructure
Previous work experience / Co-op preferred
Local candidates to MA preferred - no relocation provided

Design Verification Engineer Resume Examples & Samples

Carry out testplanning and execution of testplan
Cooperate with design team members to effectively test, verify, and debug DUT for successful tapeout
Hands-on experience with HVL and HDL languages and tools, scripting and programming languages (verilog, SV, C++, Perl, etc.)
Proficient in object oriented programming
Good understanding of random stimulus generation methodology
Networking knowledge preferred, but not essential

Pre-silicon Design Verification Engineer Resume Examples & Samples

Thoughtful and perceptive analytical ability
A genuine curiosity for understanding the system
Dedicated and committed to creative problem solving and getting things done
Computer Architecture
Object Oriented Programming
Data Structures
Experience in Ethernet or networking
Experience in Verilog, System Verilog and VHDL
Knowledge in Perl or Python

Fpga Design / Verification Engineer Resume Examples & Samples

Specification and design of verification frameworks for simulation and testing of FPGA sub-systems used in X-Ray imaging detector systems
RTL design for use within multiple projects and co-ordination of activities with other engineers and designers as required. To understand the FPGA, ASIC and microcontroller design requirements for new products and to develop a functional specification for these
Working within an interdisciplinary project team to resolve any issues involving the ASIC and FPGA system’s performance, development time schedules and resourcing requirements
Design and analysis of FPGA’s for complex programmable devices and systems of devices
Design of communication and data transfer sub-systems to imaging industry standards
Development of prototypes, performance and verification testing
Development of version control and automated build environments
Supporting compliance, regulatory and quality requirements related to design activities
Engaging in all phases of new product introduction, including concept, architecture documentation, design, prototype, test, supplier interfaces, and manufacturing introduction
Bachelor of Science or equivalent in Electronics/Physics/Engineering with a Computing bias
Extensive experience in VHDL and/or Verilog RTL
Demonstrable experience in version control
Experience in FPGA design flow for high-speed designs
Demonstrable ASIC and/or FPGA design experience in volume deployed products
Experience in system test/debug using emulators, logic analysers etc
Experience in performing detailed design analysis and calculations to meet target requirements
Proven ability to develop timely and effective solutions for challenging design problems
Experience making design trade-offs between functionality, quality and cost
Strong knowledge in CAD design tools such as Modelsim, etc
Experience in debugging FPGA-based designs using embedded debug tools (e.g. Xilinx Chipscope)
Design for high speed signal integrity and EMC compliance

Senior IC Design Verification Engineer Resume Examples & Samples

Develop patterns and regressions to increase the function coverage for all DRAM architectures and features
Provide support to design engineers, simulate, analyze and debug current chip designs
Create new methods and flows to guide DRAM chip design from verification view
Co-work with international colleagues on developing new verification tools and flows for the verification difficulties on DRAM chip
Maintain technical expertise and train circuit design engineers on new simulation tools and techniques

100

IP Frontend Design & Verification Engineer Resume Examples & Samples

Logic design, implementation & verification by Verilog for IPs and SOC development
Participate in the complex SoC design project based on ARM cores at advanced technology, complete the task assignment on time with good quality
Testbench generation, verification test pattern development and simulation on module/chip level, using Verilog, System Verilog, C/C++ and other verification languages
Participate in logic synthesis, DFT, timing analysis and closure
Independently solve technical issues and find the solutions
Write the technical documents/papers as required
Cooperate with and provide support to other functional teams (S&A,SW,TE/PE) in the NPI execution

101

IC Design Verification Engineer Resume Examples & Samples

Bachelor Degree in Electrical & Electronics Engineering
5 years of hands-on experience with System Verilog/UVM
Strong understanding of the verification process from test plan to coverage completion
Strong communication and Analytical skills
Understanding of HDL (Verilog, VHDL)
Experience in designing with FPGA using Vivado is a plus

102

IC Design Verification Engineer Resume Examples & Samples

Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering
Strong understanding of verification process from test plan to coverage completion
Experience with designing with FPGA using Vivado is a plus

103

Design Verification Engineer Resume Examples & Samples

Pro-actively design experiments to verify the optical performance of our products and identify non-conformances to speicifications
Write and maintain LabView software code to automate the data collection and processing tasks for these experiments
Analyse results and provide recommendations to Product Engineering teams in order to improve product quality or to meet design intent
Provide prompt, clear and accurate reports to support customers’ requests, both internal and external
Physics / Electrical Engineering / Photonics Degree or equivalent
Experienced in optics lab work and the use of fibre-optic test equipment
LabView or similar test equipment automation programming experience
Knowledge of optical communications
Electronics knowledge

104

Asic Design / Verification Engineer Resume Examples & Samples

Design and/or verification experience
Exposure to System Verilog, VMM or OVM
Knowledge of IC Design flows
Unix, Perl and Tcl Scripting Knowledge
Knowledge of DDR/PCI Express protocols would be advantageous · Good problem solving and communication skills
Short term travel to the US will occasionally be required (typically a 1 week period)

105

Design Verification Engineer Intern Resume Examples & Samples

Knowledge of and experience with SystemVerilog-UVM
Experience using scripting to report generation, etc
Familiarity with Verilog
Knowledge of TCL

106

SSD Design Verification Engineer Resume Examples & Samples

Understanding design specification and creating verification plan and test plan accordingly
Debugging failure cases and figuring out the root causes independently, and working with designers to fix and verify bugs
Achieving coverage goals before tape-out
1 to 5 years work experience in ASIC verification
Experience in developing block or chip level test benches, test plan creation
Experience with C/C++/System Verilog/UVM
Excellent problem analysis and debugging skills
Good potential and willing to embrace new technical challenges
Prior experience on emulation flow and methodology (Preferred)
The ability to be a team player, self-starter flexible, communicate well and understand what it takes to get the job done
Excellent English written, verbal and presentation skills

107

SoC Design & Verification Engineer Resume Examples & Samples

Discuss with system and market on the project requirement and definition
Designs and develops digital circuits for micro-controller and application processor
Verification in module level and chip level; define and execute verification plan with full functional coverage
Involved in the Digital IP design and verification, joins the SoC development for ARM Based MCU
RTL coding, integration and verification
Work with backend team on timing closure
Doing simulation in gate Level, transistor Level (full-chip spice)
Create function test patterns for test engineering

108

Senior Ic-design Verification Engineer Resume Examples & Samples

Architect and develop verification environment and testbench components such as BFMs and checkers
Develop comprehensive test plan and implement test cases
Verify design in block and chip level environment using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification
Perform RTL code coverage, assertion coverage, and gate level simulations
Drive and adopt new verification methodologies and flows for efficiency improvements
Mentor junior engineers on project execution

109

Senior Pmic Digital Design & Verification Engineer Resume Examples & Samples

Expert know how in digital design including micro-architecture definition, RTL design, and low power design
Expert knowhow in pre-silicon verification, i.e. understanding of various methodologies e.g. formal verification, constrained-random verification, UVM methodology, coverage driven verification, the ability to apply appropriate methods for given challenges and hands-on experience
Expert knowhow in semicustom digital design flow and its constraints
Experience in collaboration with concept engineering to define systems
Experience in collaboration with physical implementation
Hands-on experience in cross-skill or cross-chip problem solving
Basic knowledge in analog/mixed signal CMOS circuits would be desirable

110

Design Verification Engineer Resume Examples & Samples

Required: Advanced knowledge of SystemVerilog test-bench language and UVM
Required: Experience developing scalable and portable test-benches
Required: Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
Strongly Preferred: Experience with serial protocols such as PCIe or USB
Preferred: Excellent knowledge of one of the scripting languages: Python, Perl, TCL

111

Senior Digital Design & Verification Engineer Resume Examples & Samples

Requirements and specifications, micro-architectural definition, digital (RTL) design and verification, formal verification, gate-level simulations, and power estimation and optimization
Project deliverables may include specification documents, micro-architecture designs, RTL code, simulation models, test benches, timing constraints, UPF files, and associated documentation and additional collateral
Problem-solving skills with appropriate attention to detail; strong interpersonal, written and verbal communication skills; ability to work in a dynamic and team-oriented environment
VHDL/Verilog RTL design, simulation and verification for ASIC and/or FPGA platforms
ASIC synthesis, formal verification, gate level simulation, static timing analysis, UPF simulations, and/or power estimation
Experience with revision control systems such as ClearCase or GIT
Debug and analysis skills
15+ Years of relevant industry experience

112

Asic Design / Verification Engineer Resume Examples & Samples

Block level and/or Full chip verification experience on at least one ASIC or FPGA
Hands on knowledge of chip bus interfaces such as AHB/I2C/PCI and various standard peripherals & interfaces using Verilog/VHDL
Hands-on experience in developing testbenches and tests
Experience in UVM/OVM or other such standard verification environments
Verification concepts such as functional and code coverage
Knowledge of System Verilog Assertions

113

Senior Asic Design / Verification Engineer Resume Examples & Samples

5+ years related work experience
Bachelor or Master's degree in Electrical/Computer Engineering or equivalent
Experience with writing and interpreting synthesizable RTL code (VHDL and Verilog) is required, and experience with System Verilog is desired
Working knowledge of design and verification tools such as Cadence Incisive Enterprise Simulator, Cadence Jasper, Conformal, or similar tools
Experience with of embedded processors such as MIPS interAptiv or M14K
Experience with advanced verification methodologies, formal verification and UVM
Scripting and programming skills using csh, bash, perl, python, tcl, etc
Protocol knowledge and experience in SAS/SATA and/or PCI-Express will be an asset
Good verbal and written communication skills in English will be an asset
Excellent teamwork and time management skills, self-direction, the ability to work under pressure and the desire to excel in a competitive environment

114

Design Verification Engineer Resume Examples & Samples

Thoroughly understand design specs and develop verification plans for various designs
Develop and maintain testbenches
Run directed and constrained-random verification tests
Be able to think through design corner cases and be able to write relevant cover points
Collaborate with digital design team to debug test cases and deliver functionally correct designs
Close coverage measures to identify verification holes and to show progress towards tape-out
Create programming sequences for lab characterization and ATE
5+ years of relevant experience in digital design and/or verification
3+ years of experience developing verification collateral in Verilog, System Verilog and UVM

115

Design Verification Engineer Resume Examples & Samples

Block and system verification on Sabre SSD controller
Create test plans for full chip that includes complex reusable Intellectual Property design
Architect and implement test-bench for full chip and block level verification
Code test benches using Verilog, System Verilog, and C Program Language Interface
Provide hardware design and Field Programmable Gate Array simulation for hardware bring-up
Assist in verification of new System on Chip architectures, functions and components
Experience in SSD SoC controller architecture
Experience with Universal Verification Methodology (UVM) Testbench, System Verilog logic simulation, DPIs and C
Experience writing firmware like test programs to run on embedded processors for SSD controller engines
Experience with Serial Port Interface modeling, Joint Test Action Group modeling (JTAG)
Experience with Automated Test Equipment (ATE) silicon testing sequence programs
Experience writing tests on ARM processor cores
Experience with CPF/UPF based simulation
Experience with AMBA bus protocols
Experience with debugging simulations using simvision/Verdi
Experience with PCIe/NAND/SPI/UART/DDR interfaces
Experience with gate level simulations with SDF
Experience with FPGA simulations
Ability to work evenings or weekends, if necessary

116

IC Design Verification Engineer Wifi MAC Resume Examples & Samples

Typically requires a BSCS/BSEE degree and 14 years of related experience, an MSCS/MSEE degree and 12 years of related experience
Experience in networking, IP Verification, UVM, C, C++, tcl, systemC , python etc is highly desirable
Must have experience with Verilog, System Verilog, UVM
Experience with embedding assertions (SVA or PSL) in RTL designs is desirable, as is
Knowledge of Perl, Python, TCL or other scripting languages is desirable
Ability to effectively collaborate with multiple teams, across geographies, in a dynamic, fast paced development environment
Capability to learn new skills or technologies as needed and be self-motivated

117

Design Verification Engineer Resume Examples & Samples

Strong analytical engineering skills are required
Creative design application of engineering principles
Excellent testing and "hands on" development aptitude
Ability to oversee testing and produce final reports
The ability to work effectively in both a team setting and individually

118

Design Verification Engineer Resume Examples & Samples

Oversees definition, design, verification, and documentation for SoC System on a Chip development
Experience with Perl and UNIX would
Knowledge of microprocessor architecture, Design For Test DFT principles, Ethernet protocol, PCIe protocol

119

Senior Asic Design & Verification Engineer Resume Examples & Samples

Perform synthesis and timing closure
MS in EE with 3+ years of work experience in SOC/ASIC/IP development
Must have knowledge and experience of HDL in behavioral and RTL coding, Verilog preferred
Knowledge of UVM and System Verilog is required
Background in PCIe and ARM CPU core is a plus
Strong problem solving and debugging skills

120

Design Verification Engineer Resume Examples & Samples

This person will be responsible for some design and testing pump systems in our pumping platforms in both Enteral and IV pumping applications
Proficient in Solidworks. This person must be a “go to” engineer capable of taking on multiple projects and driving them to completion, including documentation and all other details, with little or no supervision. Experience in medical devices with FDA’s QSR, MDD, and general risk management is strongly encouraged
2-5 years Design Engineering and/or V+V experience
Worked in medical environment
Electromechanical system level testing
Experience writing plan documents
Experience writing test protocols and reports, with rationale for sample sizes, test environments, etc
Solidworks solid modeling competency
BS Mechanical, Biomedical or similar engineering degree (advance degree candidate acceptable (MS, PhD)

121

Principal Physical Design Verification Engineer Resume Examples & Samples

Developing physical verification flows
Implementing DRC, LVS, ERC and other layout post processing rules set
Developing and executing regression test plans, utilities and scripts to
Demonstrate experience working with Python/Tcl/Perl , UNIX, C++ and Make
Synopsys ICV tool suite

122

IC Design Verification Engineer Resume Examples & Samples

Architect block and full-chip verification environments using HVLs and constrained random techniques (like UVM/OVM) for SOCs with embedded CPUs and mixed signal interfaces
Develop test plans and coverage metrics from specifications and write block and chip-level tests
Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC
Replicate silicon bugs in simulation environment and validate fixes or SW workarounds
Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup
Evaluate latest verification methodologies and develop scripts etc. to automate verification flows. Work on low power DV with UPF MVSIMs and power threaded netlist sims
Assist in the development of embedded FW, post-silicon bring up

123

Senior Medical Device Design Verification Engineer Resume Examples & Samples

Requires Bachelor’s degree in ME, EE, IE, OE, BME, CE or other relevant field with 8+ years of experience in the design, development and manufacturing of a product (device, part, component, etc.), preferably in the medical device industry
Pressure Guide Wire and IVUS catheter or equivalent disposable medical device experience, especially skilled in design control process and deliverables
Must be able to read/write and speak English
Strong technical writing skills for generation of specifications, build method, work instructions, technical protocols and reports
Strong communication skills both written and verbal to provide updates and feedback to management and team members
Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Use data to drive decisions
Product transfer experience with strong understanding of product transfers from R&D to high volume manufacturing
Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors
Proficient with Microsoft Office products (Outlook, Excel, PowerPoint, Word, Visio, Project) to create schedules, presentations, graphs and charts and doing analysis
Demonstrates strong organizational and interpersonal skills working in a cross-functional, regulated environment
Proficient with additional software packages as required such as statistics software
Demonstrate organizational and interpersonal skills working in a cross-functional, regulated environment
Knowledge of testing methods at all levels (unit, integration, system, V&V, acceptance) applied within the development lifecycle
Test automation experience is a plus
Provide guidance and training to production operators
Pressure Guide Wire, Catheter or related technology experience
Solidworks/ CAD (Drawings understanding)
Requirement and test management tools (such as Doors, HPALM)

124

SOC Design Verification Engineer Resume Examples & Samples

Architectural specification review
Verification planning and architecture
Pre-silicon functional verification using the Universal Verification Methodology (UVM) and random-constrained, coverage-driven techniques
Close interaction with the logic design and firmware teams
Development of class-based SystemVerilog models
Verification methodology development and improvement
Random-constrained, coverage-driven verification
Industry standard verification methodologies like OVM, VMM, eRM and UVM (UVM preferred)
Formal Property Verification

125

Asic Design Verification Engineer Resume Examples & Samples

In-depth understanding of programmable forwarding hardware architectures
Strong technical foundation in networking
Strong C/C++ and python programming skills
Experience in L2 and L3 Ethernet switching and routing protocols (some or all of the following protocols; BGP, IS-IS, Fabric Path/Trill, IGMP, OSPF, STP, LACP, LLDP)
Experience in tunnel protocols. IPinIP, MPLS, VxLAN, L2VPN/L3VPN
Experience in VM technology. 802.1BR. VEPA and Cisco VNTAG
Experience in FCoE, QoS, sFlow, SPAN, BFD. Cisco vPC
Experience in SDN, NFV technology
Experience in ACL, netflow and Policy based forwarding
Hands on experience on switch/router embedded system software development
Strong problem solving and software development/troubleshooting skills
4+ years of related work experience is required
Experience with high availability related to switch/router products is a plus
Experience in data center fabrics and corresponding technologies like VxLAN is a plus
Experience in the forwarding model validation

126

Design Verification Engineer Resume Examples & Samples

Masters degree in EE is preferred
Experience in the development of wireless technologies is desired
Strong tapeout experience

127

Design Verification Engineer Resume Examples & Samples

FPGA, ASIC or custom IC designs
System Verilog, OVM/VMM/UVM and C/C++
Create and document verification plans

128

Design Verification Engineer Resume Examples & Samples

Verify and validate that our hardware and software solutions will achieve the functionality needed to enable our customers
Develop a deep understanding of the end customer requirements, including software applications, use models, system architecture and the SoC architecture/micro-architecture of our solutions
Lead our work in the area of DDR technology
Develop multi-faceted verification/validation strategies and plans that include advanced design verification, FPGA, emulation, software and full system testing
Define and implement leading edge verification/validation methodologies including using the cloud to enable breakthrough productivity
Efficiently execute test plans on multiple platforms, measure progress and metrics, and work with cross-functional teams to achieve these results
5+ years of experience in the area of DDR technology in the full development cycle from design to software to bring-up to system testing and optimization of performance
Experience using multiple verification platforms: test bench, emulator, FPGA, software environments and system testing
Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design
Successfully verified multiple projects working with multiple level of logic: IP blocks to SoCs to full system testing
Proficient with industry standard tools and scripting languages for automation
Good understanding and knowledge of object oriented programming concepts
Able to think big to define breakthrough methodologies
Experience with transaction level modeling

129

Design Verification Engineer Resume Examples & Samples

Develop a deep understanding of the customer requirements and the architecture/micro-architecture of our solutions
Efficiently execute test plans on multiple platforms, measure progress and metrics and have a clear understanding of the functionality this enables
· BS degree or higher in EE, CE, or CS
· 5 years or more of practical semiconductor design verification experience including System Verilog, UVM and coverage driven verification
· Experience working at multiple levels of verification: unit test bench, emulation, FPGA, software environments and system testing
Strong debug skills

130

Digital Design & Verification Engineer Resume Examples & Samples

Execute formal and functional verification, synthesisand static timing analysis
Support post-silicon validationin the lab
Implement advanced verification techniques(constrained random testing, assertions, coverage)

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