Senior Design Verification Engineer Resume Samples

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L Thompson

Loyal

Thompson

570 Demario Parks

Dallas

+1 (555) 669 0326

570 Demario Parks

Dallas

Phone

p +1 (555) 669 0326

Experience Experience

San Francisco, CA

Senior Design Verification Engineer

San Francisco, CA

Ziemann Group

San Francisco, CA

Senior Design Verification Engineer

Work with CSI HQSE and CSI Product Development Teams to manage the Life Cycle of the deployed servers
Develop test plans and coverage metrics from specifications, write block and chip-level tests, and execute the test plans from start to finish
Develop and improve existing verification regression environments
Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes
Develop block level test bench and tests in UVM methodology including scoreboard
Support continuous improvement through optimum level of process, procedures and documentations
Work with HQSE, CSI Dev and DC OPs to prepare our servers for service in the field

Houston, TX

Senior Design / Verification Engineer

Houston, TX

Wunsch-Langworth

Houston, TX

Senior Design / Verification Engineer

Designing, implementing and verifying high performance, low power IP in Verilog RTL
Driving the unit team to ensure the quality of the design work done along with on time delivery
Creating and reviewing design and verification documentation
Testing and debugging Verilog RTL
Coaching and mentoring junior engineers
Designing and implementing verification IP and testbenches using UVM
Genuine passion for technology, actively following emerging technologies and trends

present

Detroit, MI

Senior. / Design Verification Engineer

Detroit, MI

Goodwin, Heathcote and Krajcik

present

Detroit, MI

Senior. / Design Verification Engineer

present

Create verification plans based on design specifications
Develop the NAND model based on the NAND chips
Develop the verification methodologies based on SV/UVM
Develop test cases and maintain testbench/regression
A high-level of self-motivation and a proactive approach to solving problems
Good background in Verilog/SystemVerilog and verification methodology; knowledge of C or other HVL a plus
Proven track record for successful verification of IC products

Education Education

Bachelor’s Degree in Electrical Engineering

Cornell University

Bachelor’s Degree in Electrical Engineering

Skills Skills

Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality
Strong analytical and problem solving skills;, excellent verbal and written communication skills
Strong analytical and problem solving skills with pronounced attention to detail
Proficient in object oriented programming
Strong background in ASIC Design flow
Good communication and teamwork skills
5+ years of hands-on experience (testing, validation, design, repair, sustaining or service) in an enterprise or cloud server datacenter environment with x64 Industry Standard Server or related products from OEMs or ODMs
Good problem solving skills
UVM knowledge
Good understanding of random stimulus generation methodology

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15 Senior Design Verification Engineer resume templates

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Senior Design Verification Engineer Resume Examples & Samples

BS degree in Electronics or Computer Engineering with 3 to 5 years of experience or BS + MS degree with 2 to 3 years of experience
Strong background in ASIC Design flow
Proficient in Verilog, C++ and System Verilog
Experience with Design Verification methodologies including UVM, OVM or VMM

Senior Design Verification Engineer Resume Examples & Samples

Work with HQSE, CSI Dev and DC OPs to prepare our servers for service in the field
Support development, review and maintenance of field documentation, service guides etc
Support reviews of SKUs, CRDs and BOMs of various deployments
Support DC OPs training and ongoing education effort
Engineering support of large scale integration through OEM/ODM Integration factories
Engineering support of large scale server deployments into the datacenters
Support validation activities in a lab and pilot environments
Interface and interact with servers and infrastructure through the management network to root cause server fleet issues to minimize server downtime. This involves remote management as well as on-site debugging
Work with CSI HQSE and CSI Product Development Teams to manage the Life Cycle of the deployed servers
Maintain best practice communications between CSI, MCIO and other teams and vendors to enhance the quality and reliability of the infrastructure going forward
Support technical problem resolution in all phases through diagnostic tools and automation (scripting) using C, C++, C#, PowerShell, Python, Perl and/or terminal emulator scripts
Use the developed tool automation to check and then work with Microsoft Product Groups to deploy Server FW (BIOS, BMC, Chassis Manager etc.) and OS images with associated configuration settings
Triage and document bugs (during deployment as well as sustenance phase) through TFS (Team Foundation Server), and then work with HQSE, CSI engineering, and MCIO teams to root cause and resolve
Support continuous improvement through optimum level of process, procedures and documentations
Bachelor of Science in Electrical/Computer Engineering or Computer Science, or comparable degree preferred
5+ years of hands-on experience (testing, validation, design, repair, sustaining or service) in an enterprise or cloud server datacenter environment with x64 Industry Standard Server or related products from OEMs or ODMs
Hands on Programming skills with C, C++ or C# desired, scripting skill using PowerShell, Python or Perl is essential
Strong grasp of key technologies in servers such as CPU, motherboards, BIOS, BMC, remote management, memory, storage sub-system is required
Hands on experience of operating in Windows Server 2012 environment and imaging tools (System Center, WDS etc.) is essential. Experience with Linux is a plus
Passion for server deployments and problem solving in a high volume data center environment is essential
Must be willing to travel to integration factories or data centers as necessary for On-Site support
Individual effectiveness skills such as discipline, time management, decision making, planning and organizing work, summarizing results through technical reports (TFS, MS Office) are vital
Must be able to communicate technical concepts and solutions effectively to a broad audience
Self-motivated individual, must be able work independently as well as collaboratively in a team environment
Must be able to plan work, and work to a plan; adapting as necessary in a rapidly evolving Environment

Senior Design Verification Engineer Resume Examples & Samples

Good understanding of HW architecture and validation methodology
At least 4-7 years of experience in product validation on consumer devices that actually shipped
A self-starter who can work across silicon, system and software teams to identify the tools, test cases and execute
Experience in C/C++ and should be able to adapt to developing tests with multiple test environments
Should be hands on in lab debug, should know to use analyzers and scope to understand bus interfaces and signal integrity
Must have a curious mind-set to break and debug designs
Good working knowledge of system-boot procedures, BIOS, operating system and drivers and how the whole flow helps with hardware validation is a plus
Experience with validating specific sub-components like micro display, audio and sensors is a definite plus
Pre-silicon verification and design experience is a plus
Good communication and written skills are a must

Senior Design Verification Engineer Resume Examples & Samples

As a member of the design verification team, the candidate will be responsible for the complete end to end validation of our products to ensure a fantastic user experiences. The candidate will participate in the development of our products from product inception to mass production
Triage and evaluation of complex subsystems leading to clear action plans and customer impact across hardware, software drivers, applications and protocols
Capable of working with cross-functional teams to define, implement and triage system level tests
Minimum BSEE/BSCE with 5-10 years of experience
Familiar with sensors and how to test them
A successful candidate must be able to implement and run a test plan
Familiarity with automation and scripting languages
Familiarity with low power mobile devices is a plus

Senior Design Verification Engineer Resume Examples & Samples

MSEE/CS with up to 10-15 years of experience in SOC or ASIC verification
Experience in developing or contributing to verification flows and methodologies
Expertise in System Verilog or equivalent object oriented verification methodologies such as VMM or UVM
Experience in full chip validation techniques
Experience in Gate Level Simulations concepts
Experience in writing and executing on complex testplans of both functional blocks and full chip
Experience on standard protocols such as DDR2/3, PCI-E/SATA/USB/Ethernet etc
Ability to write and architecting protocol checkers, BFMs and knows automation concepts (PERL, Python, etc)

Senior Design Verification Engineer Resume Examples & Samples

The Design Verification Engineer role involves various aspects of verification of cutting-edge optical transceiver/transponders and its applications at system level
Identify, define, write and execute test cases for comprehensive and effective module level performance validation. Various operation conditions will be covered such as interface environment, service disruption, etc
Analyze test results, identify root cause, and actively make sound recommendations to resolve issues
Automate test procedures and analysis tools
Interfacing with field application engineering team, understanding customer specific application issues and continuously improving verification testing coverage
Provide leadership and guidance to junior Engineers where needed
BS (5 yrs experience) or MS (2+ yrs experience) in EE/Engr. Physics or equivalent field
Knowledge of modern analog and digital circuits
Strong background in verification methodology and test bench development
Familiar with industry standards (IEEE, ITU.T, FC-PI, etc.) and MSAs
Experience in engineering test processes (designing and automating, writing test plans and writing test reports)
Hands on lab debugging/measuring skills using oscilloscopes, communication analyzers, logic analyzers, etc
Prior programming experiences with scripting languages such as Python, Perl, etc
Must be self-motivated, effective team player able to thrive in a fast-paced engineering environment
Strong analytical and problem solving skills;, excellent verbal and written communication skills
Experience with optical communication systems a plus

Senior Design Verification Engineer Resume Examples & Samples

Candidate should possess a Bachelor's in Electrical Engineering or Computer Science with 7 years and/or a Master's degree in Electrical Engineering or Computer Science or similar degree with 5 years of relevant industry experience
Good knowledge of reuse concepts
Adept in programming and/or scripting (C++, Perl* and others)
· Experience with logic design is Preferred
· 8+ Years of relevant industry experience

Senior Design Verification Engineer Resume Examples & Samples

7+ years verification experience
Expertise in HVL and HDL (SystemVerilog, Verilog)
Advanced knowledge of HVL methodology (UVM/OVM)
Solid verification skills in problem solving, constrained random testing, and debugging
Experience writing scripts in languages such as Perl or Python
Knowledge of industry standard interfaces
Experience with low-level programming of systems in C/assembly a plus
Experience defining coverage space and writing coverage model a plus
Experience with SystemVerilog Assertion (SVA) a plus
Should be a team player with excellent communication skills and the desire to take on diverse challenges

Senior Design Verification Engineer, CSM Resume Examples & Samples

Advanced knowledge of SOC/Display/Audio & System architecture/design & in-depth knowledge of the state of the art verification flow
Experience with low-level programming in C/C++/assembly
Clear understanding of constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
Knowledge of Formal verification, Hardware acceleration all a plus

Senior Design Verification Engineer Resume Examples & Samples

Develop FPGA Design Verification tests, and test plans
Execute tests, analyze results, review RTL, determine probably source of failures, write bug reports
Expertise in system Verilog, and UVM
Developed and used scripting languages such as TCL, Perl, and Python
Experience with bug tracking (e.g. bugzilla), revision control (e.g. git), and build systems (e.g. make)
Working knowledge of logic design using RTL techniques
Familiar with Protocols and VIPs for PCIe, Ethernet, DRAM

Senior Design Verification Engineer Resume Examples & Samples

3+ yrs hand-on experience in full-chip/sub module design verification for high performance SoC
Good understanding of hardware architecture and hand-on skills in verilog, system verilog, UVM simulation environment
Good communication skill and experience working with asic design and software teams

Senior Design Verification Engineer Resume Examples & Samples

BS w/ 5 years or MS w/ 2 in Electrical Engineering, Computer Engineering, or Computer Science
Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip SOCs and FPGAs
Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus
Verification Experience in protocols like AXI, DDR4, HBM, PCIe, Processors, Graphics is a plus
Experience with FPGA programming and software is a plus

Senior Design Verification Engineer Resume Examples & Samples

Will be working with a team of design and verification engineers and play an important role in the verification of a next generation DSP architecture in Silicon
Work with Architecture, design and software teams to create block and subsystem level verification testplans and develop testcases for verifying next generation multi-core DSP processors
Create testbenches, testplans and testcases starting from the architecture/ implementation specification, and work with architecture, design, verification and software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
Debug failures in simulation / emulation of the design on multiple platforms and assist in identifying / obtaining and verifying design changes
Bachelors or Masters in electrical or computer engineering
5 years of experience in the area of processor / SoC verification
Experience in verification of one or more of the following: multi-core processors including SIMD, Vector processors, floating point, etc. is a plus
Experience in SoC verification a plus
Ability to debug failures in RTL and enviroment on different verification platforms
Strong analytical problem solving, and attention to details
Expertise in Verilog/System Verilog, C/C /SystemC, UVM, Scripting languages like Perl/Python, etc

Senior Design Verification Engineer Resume Examples & Samples

Play a key role in verifying the performance of the architecture and design
7 years of experience in the area of DSP/vector processors, SIMD/GPU/CPU, etc
Experience in verification of one or more of the following: multi-core processors including SIMD, Vector processors, floating point, etc
Good understanding of compilers and tools for DSP processors preferred

Senior Design Verification Engineer Resume Examples & Samples

Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and function coverage with design team
Good understanding of object oriented programming concepts
Prior experience in verification of cache sub systems in processors and/or cache coherent interconnect
Prior experience in verifying is system/sub system level involving multiple blocks
Prior experience with protocols such as AXI,APB,AHB etc
Programming in scripting languages like Python, TCL and Perl
Good problem solving skills and analytical ability
Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc

Senior Design Verification Engineer Resume Examples & Samples

Create block level verification plan, test plans and full chip test plan
Develop block level test bench and tests in UVM methodology including scoreboard
Come up with verification strategy to verify the system level coherency and execute on it
Performance analysis of cache implementation protocols
Work on subsystem level verification
Work with designers to get the coverage closure
Port the block level tests to full chip test bench
Integrate VIPs as needed
Work with software, validation and emulation teams as needed
Work on other aspects of verification like CDC, gate simulation
Work on lab bring up and silicon validation

Senior Design & Verification Engineer Resume Examples & Samples

Experience of block level RTL design and verification for non-trivial FPGA/ASIC developments
Competency in hardware design and verification languages, preferably Verilog and System Verilog / UVM
Experience producing specifications and documentation describing designs
Proficiency in scripting languages, e.g. Perl/TCL/Python
At ARM, we are proud to have a set of behaviours that reflect our unique culture and guide our decisions, defining how we work together to defy ordinary and shape extraordinary. These behaviours are assessed as part of the recruitment process
Partner and customer focus
Team and personal development
Deliver on your promises

Senior Design Verification Engineer Resume Examples & Samples

Prior understanding of microcontroller architectures and products
Experience with Object Oriented Programming languages
Experience with Python/Perl or other scripting languages
Ability to work with globally distributed teams

Senior Design / Verification Engineer Resume Examples & Samples

Designing, implementing and verifying high performance, low power IP in Verilog RTL
Testing and debugging Verilog RTL
Designing and implementing verification IP and testbenches using UVM
Plan and track design tasks to meet the targets at the planned time
Driving the unit team to ensure the quality of the design work done along with on time delivery
Coaching and mentoring junior engineers
Experience of block level RTL design and/or verification for non-trivial FPGA/ASIC developments
Proficiency in hardware design and verification languages, preferably Verilog and/or System Verilog/UVM
Fluency in both written and oral English
Experience producing specifications and documentation describing complex designs
Some team leadership experience, including planning and managing tasks
Genuine passion for technology, actively following emerging technologies and trends
Practical experience of working on microprocessor or complex system interconnect and peripheral designs
Experience of verification and design for verification techniques
Knowledge of formal verification techniques and tools
Familiarity of Unix/Linux working environment
Line management experience

Senior. / Design Verification Engineer Resume Examples & Samples

Create verification plans based on design specifications
Develop the NAND model based on the NAND chips
Develop test cases and maintain testbench/regression
Develop assertions, coverage, and partly work on NAND firmware validation if needed
Develop the verification methodologies based on SV/UVM
Support customers
Proven track record for successful verification of IC products
Good background in Verilog/SystemVerilog and verification methodology; knowledge of C or other HVL a plus
Knowledge and experience with Perl and Unix/Linux scripting strongly desired
Knowledge in writing assertions, UVM/OVM/etc a plus
A high-level of self-motivation and a proactive approach to solving problems
Good English communications skills

SSD Senior Design Verification Engineer Resume Examples & Samples

Understanding design specifications and creating verification plan and test plan
Creating test bench and test cases for storage controller blocks and system
Debugging failure cases and figuring out the root cause independently, and working with designers to fix and verify bugs
Gate simulation, timing verification and power-aware simulation
Leading and mentoring junior members
Master degree or higher, electronic engineering and computer science related majors are preferred
Above 5 years work experience in ASIC verification
Proven track record of contributing to successful tape-outs
Proficiency in advanced Verification techniques, at both a block and system level, to work with the design engineering team to support excellence in design principles and practice
Experience in developing block and chip level test benches, test plan creation
Experience with C/C++/System Verilog/UVM, coverage driven verification principles, Mentor Questasim, Power Aware verification, SVA assertion
Prior experience in storage controller verification. Experience in SATA/SAS/PCIe protocols, NAND, ARM/AXI/AHB, encryption, memory control, error management, power management. (Preferred)
Knowledge on firmware development (Preferred)
Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation (Preferred)

Senior Design Verification Engineer Resume Examples & Samples

Requires BS w/ 6+ years or MS w/ 4+ years or PhD w/ 2+ years in Electrical Engineering, Computer Engineering, or Computer Science
Requires proven track record in technical leadership and mentoring. This includes planning, execution, tracking, verification closure, and delivery to programs
Requires strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs
Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification
Verification experience in DSP, ADC/DAC, Gigabit Transceivers, AXI, HBM, DDR4, PCIe verification is a plus
Requires strong experience in full chip verification
Experience in modeling SystemC and using SystemC based models in verification is a plus
Verification experience in PCIe, Processors, Graphics is a plus
Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus

Senior Design Verification Engineer Resume Examples & Samples

Required: Advanced knowledge of System Verilog test-bench language and UVM
Strongly Preferred: Experience with mixed signal verification methodology for IPs such as PHYs, PLLs etc
Strongly Preferred: In lieu of UVM knowledge, C/C++ expert level knowledge
Preferred: Knowledge of formal verification methodology

Senior Design Verification Engineer Resume Examples & Samples

Master's Degree in Electrical Engineering or Computer Science with 8+ years of experience preferred OR
Bachelor's Degree in Electrical Engineering or Computer Science with 10+ years of experience
Experience with verification methodology and C and verification of cache coherency in system level
Block level test bench and silicon bring up and silicon validation
Experience in PCIE Gen3, AMBA AXI3/AXI4 , AMBA ACE ,or AMBA CHI-5 protocol is a plus

Senior Design Verification Engineer Resume Examples & Samples

Support of assertion and coverage-driven methodology
Technical support to verification team members in Micron’s China office
Three to ten years of experience in large scale logic design verification projects
Solid knowledge and experience in SystemVerilog object-oriented language
Experience in verification methodologies such as UVM
Experience in scripting language such as TCL and PERL
Experience in non-volatile memory designs such as NAND flash
MS degree in Electrical or Computer Engineering or equivalent

Senior Design Verification Engineer Resume Examples & Samples

Participate in architecture definition and modeling
Contribute in micro-architecture specification and reviews
Partake in verification environment architecture and methodology
Engage in post-silicon bringup and debug in the lab
Mentor and enable other engineers
Experience in high-performance ASIC verification
Good understanding of ASIC design and verification methodologies and flows
UVM knowledge a plus
Good communication skills and a team player
Complex ASIC verification experience

Senior Design Verification Engineer Resume Examples & Samples

Develop test plans and coverage metrics from specifications, write block and chip-level tests, and execute the test plans from start to finish
Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes
Develop and improve existing verification regression environments
BSc w/ 6+ years or MSc w/ 4+ years or PhD w/ 2+ years in Electrical Engineering, Computer Engineering, or Computer Science
Experience in block level NOC(Net work on Chip) verification is a plus

Senior Design Verification Engineer Resume Examples & Samples

MS/PhD EE/CS
2 years of experience in digital design/verification
Experience in digital design and digital signal processing applications
Experience in code coverage tools and debugging tools such as Verdi
Proficient in systemVerilog and UVM
Experience in using simulation tools such as Incisive, VCS and/or Questa
Experience in scripting language such as Perl, Tcl and Csh
Experience in disk drive read channel application is a plus