Design Enablement Resume Samples
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Design Enablement Resume Samples
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N Botsford
Nico
Botsford
23841 Hiram Bypass
Los Angeles
CA
+1 (555) 571 2724
23841 Hiram Bypass
Los Angeles
CA
Phone
p
+1 (555) 571 2724
Experience
Experience
Houston, TX
MTS Design Enablement
Houston, TX
Little-Bashirian
Houston, TX
MTS Design Enablement
- The DE3 team is responsible for the evaluation, development and management of new feature integration in advanced node PDKs
- Developing scripts to automate process independent test structure development and result analysis
- Works closely with the parasitic extraction modelers to ensure that both tools work seamlessly together
- Developing test structures to performed coverage, accuracy and inter tool run result consistency
- Develop methods and/or scripts to improve PDK component efficiency or accuracy
- Conduct model to hardware checking and integration in Design System model checking
- As LVS developer, you develop Calibre LVS code for CMOS technologies including FinFet, FDSOI, and bulk technologies
New York, NY
Smts Design Enablement
New York, NY
Fritsch, Casper and Hilll
New York, NY
Smts Design Enablement
- Work with partners and customers to communicate design and technology value and performances
- Work with IP Development teams and GLOBALFOUNDRIES customers to deliver world-class designs
- Work with Device teams on technology definition, development, targets, and benchmarking
- Work wit customer support engineers on customer issue resolution
- Develop and support DFM decks utilizing pattern matching methodologies
- Work with EDA tool vendors to drive tool issue resolution
- Efficient data management (compatibility and sharing)
present
Philadelphia, PA
Senior Eng Design Enablement
Philadelphia, PA
Hoeger-Kshlerin
present
Philadelphia, PA
Senior Eng Design Enablement
present
- Create, update / track ongoing development work progress & add usage guides
- Support scripting and automation to improve work efficiency
- Develop scripts and automated tools to improve the quality and cycle-time of Tapeouts
- Working closely with worldwide Device engineers on the technology development
- To create and maintain testcases for Process Design Kit elements, and perform quality assurance checks to ensure quality deliveries to customers
- Research, apply and continually improve industry and company best practices surrounding OPC development
- Collaboration with PDK Library, technology development, test-site layout & developers across global organization
Education
Education
Bachelor’s Degree in Electrical Engineering
Bachelor’s Degree in Electrical Engineering
University of Central Florida
Bachelor’s Degree in Electrical Engineering
Skills
Skills
- Good knowledge of SOI and bulk CMOS semiconductor processes for RF technologies on 12, 14, 22, 28, 40, 55, 65, 130 and
- Able to work as a team
- Effective communicator and good presenter
- Passion for learning new skills
- 180nm nodes
- Driven, motivated, takes initiative, adaptive and meticulous
- Systematic problem solving skills
- Familiar or has worked on foundry’s PDK and usage for deep submicrometer and/or nanometer testchip tapeouts
- Familiar with RF characterization and modeling softwares such as Agilent’s ICCAP and ADS
- Expertise in RF circuit designs, layout implementation, testing and silicon validation with models
10 Design Enablement resume templates
Read our complete resume writing guides
1
Design Enablement Engineering Professional Resume Examples & Samples
- Associate's Degree, Bachelor's Degree or College Diploma
- Basic understanding of physical layout, technology groundrules, and semiconductor processing
- Fluent English (both verbal and written) and strong communication skills
- Master's Degree in Electrical/Electronic Engineering, Computer Science, or Related Field
- At least 1 year experience in Apply Knowledge of Semiconductor Technology
- At least 1 year experience in Computer Engineering
- Basic knowledge in Design Automation tools such as Mentor Graphics Calibre, Synopsys StarRC, or Cadence Virtuoso
2
Foundry Design Enablement Manager Resume Examples & Samples
- Bachelor's degree in Electrical Engineering, Computer Engineering or closely related technical field
- Four years of experience with microelectronics enablement or design -OR- closely related experience in microelectronics process/product development
- Must have some Management or Leadership experience (team lead, project lead, IPT lead, etc.)
- Ability to obtain and maintain a DoD Secret clearance. U.S. Citizenship is an eligibility requirement to obtain a DoD clearance
- Master's degree in Electrical Engineering, Computer Engineering or closely related technical field
- PDK development experience, including techfiles/pcells/DRC ruledecks/LVS ruledecks/extraction
- Knowledge of industry standard microelectronics design environments/tools, common scripting languages, as well as a demonstrated track record of successfully enabling capabilities for teams of designers
- Working knowledge of microelectronics fabrication
- Analog, Digital, Mixed Signal or RF Microelectronics Design background
- Functional and program management experience
3
MTS Design Enablement Resume Examples & Samples
- The DE3 team is responsible for the evaluation, development and management of new feature integration in advanced node PDKs
- Interaction with external customers and internal teams (PDK tool developers, fab team, program and sales/marketing organizations) to create competitive enablement solutions
- Experience in design tools, physical layout design and design/process interaction
- Solid understanding of design / process interaction
- Limited travel to customer and other company locations
- M.S. with 7 years of experience, or PhD with 5 years’ experience
- Strong interpersonal skills
4
Smts Design Enablement Resume Examples & Samples
- Collaborate with product management and systems engineering to define critical silicon PA performance requirements for next generation wide-area, local-area, ultra-low power or high throughput wireless standards
- Develop state-of-the art Silicon PA and RF Power subsystem block and subsystem level designs for emerging market RF Front End requirements
- Perform physical design and verification
- Characterize initial silicon and work with internal test resources for comprehensive testing of sufficient quantities of ICs to demonstrate achievement of critical performance requirements
- Perform all activities in a safe ad responsible manner and support all Environmental, Health, Safety & Security requirements and programs
- BS in Electrical Engineering or equivalent with Silicon (SiGe, CMOS) RF, microwave and millimeter wave PA design emphasis. Knowledge of and experience with GaAs or GaN technologies are significant and valuable
- Minimum 10 years’ RF power design and product experience
- Design experience with state of the art next generation wireless standards and modulation schemes with implications for RF power devices
- Experience with 3GPP and /or 802.11 specifications
- Ability to work with early release PDKs
- If you need a reasonable accommodation for any part of the employment process, please contact us by email at usaccommodations@globalfoundries.com and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address
- GLOBALFOUNDRIES is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, gender identity, national origin, disability, or protected Veteran status
5
Design Enablement Resume Examples & Samples
- Engineer and validate PDK component requirements via interlock with others, e.g. Ground Rule and Device engineers
- Minimum of 6 years of work experience in semiconductor and/or EDA industries
- Master’s Degree in Electrical Engineering, Microelectronics, or equivalent
- Familiarity with GLOBALFOUNDRIES process technology is preferred.Excellent technical problem solving skills
- Outstanding communication skills – both written and verbal; demonstrated ability to communicate at various levels within an organization
- Good attitude and interpersonal skills, tactful and works well in team environment
- Self-motivated, resourceful, shows initiative and needs minimum supervision; well organized and exhibits attention to detail
- Demonstrated hands on PDK developer-level experience in the development and testing of DRC rule files
- Ability to interpret complex design rules
- Hands on experience in TCL and shell programming
- Experience with Mentor Calibre physical verification tools
6
Design Enablement Engineer Resume Examples & Samples
- To bridge integration to design through process-design interactions understanding including the intersection of technology ground rules and process fail modes
- To define test structures for test chip vehicles that capture critical process fail modes to enable rapid technology learning for improved yield and performance. To ensure proper implementation of test structure construct on test chip vehicles
- To analyze test structure data to investigate process systematic yield/performance detractors, determine root cause, and guide implementation of experiments to improve process quality, increase product yield and performance, and reduce undesired systematic issues
- Communicate effectively (written and verbal)
- PhD in Electrical Engineering, Material Science& Engineering or Chemical Engineering degrees preferred
- 4 years relevant experience
7
Senior Eng Design Enablement Resume Examples & Samples
- Interpret process design rules, specifications (p-cell, floor-plan) for device/macro creation
- Through physical verification / validation of all device/macro components of PDK test-site before tape-out
- Closely engage with compact modelers, designers and ensure specifications implemented ahead of test-chip tape-out
- Collaboration with PDK Library, technology development, test-site layout & developers across global organization
- Key focus is to maintain high quality PDK enablement for GF's RFBU Foundry technologies and clients. A person in this role may interact with external Foundry Clients, Electronic Design Automation (EDA) vendors
- B.Tech / M.Tech in Electronics Engineering or VLSI
- 2+ years of direct work experience in custom layout development & verification
8
Pmts Design Enablement Resume Examples & Samples
- Create and update model release notes, model reference documents and application notes. Document any known limitations, issues, and solutions, in order to communicate relevant information on proper usage of the RF transistor model kits to GLOBALFOUNDRIES’ customers
- Hands-on experience with on-wafer DC/AC/RF/noise/large-signal characterization and de-embedding procedures using Cascade Microtech prober, Agilent’s PNA, PLTS etc
- Familiar with RF characterization and modeling softwares such as Agilent’s ICCAP and ADS
- Experience in analog/RF circuit design and/or has performed RF device layouts using Cadence
- Good knowledge of SOI and bulk CMOS semiconductor processes for RF technologies on 28, 40, 55, 65, 130 and 180nm nodes
- Driven, motivated, takes initiative, adaptive and meticulous
- Systematic problem solving skills
- Able to work as a team
- Passion for learning new skills
9
Smts Design Enablement Resume Examples & Samples
- Work through all stages of the software development life-cycle from requirements, development, test and release using Agile disciplines
- Modify existing software infrastructure to debug and correct critical issues
- Strong OO programming and design skills
- Interact with other teams such as mask recipe engineers and process engineers to obtain information on functional requirements and priorities for new features
- Maintain detailed application documentation and revision control
- Contribute to multiple projects and expert in test strategies
- Work in a dynamic collaborative environment requiring strong team skills with programmers, engineers, managers, and production employees
- Experience in OPC / RET areas and Semiconductor Process knowledge preferred
- Individuals with strong ability to learn and explore new technologies and who are able to demonstrate good analysis and problem solving skills are preferred
- Must have the ability to develop critical functionalities consistently and in a timely manner
10
MTS Design Enablement Resume Examples & Samples
- Develop and maintain cells in the PDK library for each supported device mask Layout, schematic, schematic Symbol views
- Bachelor’s in electrical engineering, microelectronics or equivalent
- 8 years of relevant experience, 5 years with Master’s, or 3 years with a PhD
- Experience running Mentor/Calibre physical verification tools for DRC and LVS
- Proficiency in Cadence SKILL++ and PAS
- Experience developing fluid guard rings
- Solid understanding of semiconductor processes, devices and their layout
- Experience running physical verification tools for DRC and LVS and interpreting results
- Self-motivated, resourceful, shows initiative and
- Needs minimum supervision
11
Dmts Design Enablement Resume Examples & Samples
- Direct the development of state-of-the art Silicon PA and RF Power subsystem block and subsystem level designs for emerging market RF Front End requirements
- Design, implement and tape-out key designs on internal test chip schedules
- Work with partners and customers to communicate design and technology value and performances
- Masters in Electrical Engineering or equivalent with Silicon (SiGe, CMOS) RF, microwave and millimeter wave PA design emphasis. Knowledge of and experience with GaAs or GaN technologies are significant and valuable
- Minimum 15 years’ RF power design and product experience
- Ability to perform mixed-signal simulation and verification of PA and antenna interface subsystems
- Experience with electromagnetic simulation tools such as Lorentz Peakview, AnSoft HFSS, Keysight Momentum, EMDS or similar
- Experience with lab characterization of standalone and integrated PAs
- PhD in Electrical Engineering or equivalent with Silicon (SiGe, CMOS) RF, microwave and millimeter
- Production level silicon PA design, associated silicon RF Power component design and/or wireless systems design with RF power expertise a plus
- Demonstrated ability to plan, manage and execute design plans with a PA design team
12
MTS Design Enablement PDK Engineer Resume Examples & Samples
- Minimum of 8 years of work experience in semiconductor or EDA industries
- Physical design experience in deep sub-micron, preferably advanced nodes
- Expertise in Cadence SKILL programming language
- Solid experience developing PDK device library components and definitions including SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation/netlisting
- Solid understanding of requirements and experience enabling schematic/connectivity driven layout
- Experience with physical verification tools for DRC and LVS
- Familiarity with GLOBALFOUNDRIES process technologies
- Experience with Cadence PAS tools
- Experience developing Fluid Pcells and custom Fluid guardrings
- Proficiency in SKILL++
- Proficiency in other scripting languages: Python, Perl, TCL, shell, etc
- Solid understanding of semiconductor processes
13
Design Enablement Engineer Resume Examples & Samples
- Define SRAM electrical specs and drive spec closure with customer
- Support SRAM device targeting for SRAMs across multiple nodes
- Work with SPICE modeling team to define model targets, provide Model QA/feedback
- Support Si vs model correlation analysis at bitcell/array level
- SRAM simulation support for customer electrical spec requests and debug
- Minimum of MS degree. Degree must be in Electrical Engineering, Materials Science, Solid State Physics or other relevant engineering physical science discipline
- Requires demonstrated knowledge of MOSFET device physics, SRAM bitcell design, and device - design interaction for SRAM arrays
- Strong abilities in working with cross-functional teams and data analysis are needed
- Demonstrated knowledge of SPICE, advanced CMOS process technology
- PhD preferred
- Knowledge of process integration and circuit design is a plus
- Excellent learning agility, analytical, interpersonal and presentation skills
- Outstanding communication skills - both written and verbal
- Strong organizational skills along with demonstrated ability to manage multiple tasks simultaneously and react to shifting priorities to meet business need
- Strong team player with ability to work well within a global team
14
Smts Design Enablement Resume Examples & Samples
- Develop and configure build scripts for building and testing of the PDK components
- Develop a configurable/scalable infrastructure to automate build and QA processes for PDKs
- Design and develop web applications to interact with the build infrastructure
- Design and develop custom tools to optimize test solutions for PDK QA
- Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety and Security requirements and programs
- BS degree in Electrical Engineering, Computer Science, Engineering or equivalent plus minimum of 8 years of experience in Software Development or Systems Engineering
- Demonstrated leadership in specification, design, and implementation of a large scale software project
- Experience with Python and/or Java programming language
- Experience with Oracle database development
- Experience with build automation using ANT
- Experience with XML development
- Proficient with Object programming and design patterns
- Experience with Unit Testing and Test Driven Development a plus
- Experience with Hudson/Jenkins a plus
- Experience with web framework a plus
- Knowledge of semiconductor design and fabrication process is a plus
- Knowledge of Process Design Kit (PDK) development process and components is a plus
15
Senior Engr, Design Enablement Resume Examples & Samples
- Delivery and maintenance of industry leading Technology PDKs
- Interpret process design rules, spice model and interconnect specifications and electrical parameter documents, to create specification data for PDK development
- Develop & verify Layout Versus Schematic LVS rules for RF technologies
- Through IP based validation of all components of PDK (compact-model verification, complete front-end device, simulation, p-cell to back-end physical design verification) before shipping kits to customers
- Automate PDK development & verification process
- Develop regression test-cases for LVS/PEX components, validate coverage for all supported vendor tools
- Closely engage with compact modelers, PDK developers, provide test-cases and ensure reported client issues are resolved before PDK release
- Collaboration with Library, technology development, test-site layout & PDK developers across global organization
- Good communication and interpersonal skills and the ability to work effectively in a cross-functional team environment
- Create, update PDK component release notes & add application usage guides for GF clients
- B.Tech / M.Tech, Masters in Electronics Engineering or VLSI
- 2+ years of experience in PDK development & verification
- Semiconductor device knowledge
- Direct experience in EDA tools Cadence Virtuoso, Cadence Assura/PVS, Mentor Calibre
- Experience working on UNIX/Linux platform
16
Smts Design Enablement Resume Examples & Samples
- Develop physical verification decks including LVS/ERC (Mentor Graphics Calibre), PEX (StarRC, xRC, xACT, QRC, and field solvers), and EMIR (Voltus/Voltus-Fi, Redhawk/Totem)
- Develop appropriate mapping/interface files to enable smooth extraction flows from LVS to PEX
- Regularly interface with Technology Development, Modeling, and Device teams to ensure proper definition of input specifications (DM, Process Assumptions, Instance Parameter Lists)
- Work with EDA tool vendors to drive tool issue resolution
- Work wit customer support engineers on customer issue resolution
- MS in Electrical Engineering, Physics, or Computer Science
- 10+ years experience in physical verification aspects of IC design flows(LVS, PEX)
- 7+ years of experience in Mentor Graphics LVS and/or other industry standard LVS tools
- 5+ years experience in StarRC, Cadence QRC and/or other industry-standard PEX tools, and PEX model generation
- 2+ years experience in Mentor Graphics PERC/PERC-LDL
- 2+ years experience in Ansys Redhawk/Totem and/or other Electromigration and IR analysis tools
- Familiar with various foundry technologies
- Aptitude to identify root cause of problems and work with multiple organizations to drive resolution
- Experienced in scripting languages such as Perl, or Tcl
- Proficient in English language, spoken and written
17
MTS Design Enablement Resume Examples & Samples
- Develop Cadence Mask Compose code to assemble Frame library elements into the required reticle floorplan and deliver the built Frame on time to meet program needs
- Lead effort to close all elements of the Frame library design/layout
- Successful candidates will work in a dynamic collaborative environment requiring strong teaming skills with programmers, engineers, managers, and production employees. It is also important to interact well with other teams such as Field Application Engineering, Product Engineering, Release Team, Technology Development, Design Enablement, Process Integration, Patterning, Metrology, Photolithography, Characterization or Design Services, to obtain information on functional requirements and priorities for new features
- Design, code, test custom Frame (Dice Lane) Infrastructure systems and applications supporting semiconductor testsites. Cadence Mask Compose is the standard tool used in this task. Experience in programming, scripting and relational databases may also be valuable
- Bachelor's Degree in sciences,
- Familiar with advanced semiconductor
- Master's Degree with minimum of 5 years of
- 5 year of professional Software Engineering with
- Knowledge of programming (JSP, Spring framework,
18
MTS Design Enablement Resume Examples & Samples
- As LVS developer, you develop Calibre LVS code for CMOS technologies including FinFet, FDSOI, and bulk technologies
- Regularly interfaces with design rule developers, process development engineers, device designers, device modelers, Design Rule Checking (DRC) coders, and client technical support engineer
- Bachelor’s Degree in Electrical Engineering or Computer science or Engineering related field
- 6+ years of experience
- 3+ years of experience in Calibre LVS and/or other industry standard LVS tool Fluency in English Language - written & verbal
- Master's Degree in Electrical Engineering or Computer science
- Knowledge of Calibre PERC language
- Experience developing automation using scripting like perl, tcl, etc
- Knowledge of device physics and circuit
- Knowledge of IC circuit design flows
19
Design Enablement Technician Resume Examples & Samples
- Coding in Visual basic software coding
- Usage of semiconductor testing/character equipment using wafer level needles/probe cards
- Backup person to submit all purchase orders for lab/department
- Great team player skills
- 0-1 years
- Associates degree in EE
- Bachelor of Science degree in EE
20
Principal Eng Design Enablement Resume Examples & Samples
- Master / PhD in Electrical Engineering
- 2+ years of relevant experience
- Team player with a global mindset
21
Eng Design Enablement Resume Examples & Samples
- Desired candidate should have good proficiency in English (verbal and written),
- Should be currently pursuing a Master’s Degree in Electronics (Microelectronics, VLSI, embedded, power etc but with a fair amount of coding skills) or IT or Computer Science with familiarity/expertise in Perl scripts and Korn Shell scripting
- Knowledge of Tcl, PHP, Oracle, MySQL and EDA experience in Mentor / Synopsis / Cadence etc will be a plus
- The project cannot be used as a topic for the candidate’s Masters thesis/report
22
Smts Design Enablement Resume Examples & Samples
- Communicate and interface with characterization, DFM and fab engineering
- BS Degree in Electrical Engineering, Computer Science, or related field with at least 4 years of relevant industry experience
- Masters and/or PhD in Engineering or related field
- Experience with semiconductor manufacturing & foundry silicon process
23
Senior Eng Design Enablement Resume Examples & Samples
- PCB design and layout for reference designs
- Application reference basic build, debug and characterization
- Lab tools automation
- Lab component inventory management
- Soldering of SMD components for debug
- Cadence Allegro, Kicad for PCB schematic/layout design
- Experience with use of oscilloscopes/DMM's power supplies
- Well versed in C++ and object oriented programming concepts. Knowledge of Visual Basic is an advantage
- Micro controller programming
- Ability to assemble application references in prototype quantity and SMD soldering for debug
24
Spring Co-op-design Enablement Resume Examples & Samples
- Uses internally developed process design kits (PDKs) as well as other physical design, layout, and verification tools to generate optical, electrical as well as overall frame structures, to enable reticle level design to be defined
- Creates frame related specification
- Support frame generation infrastructures, both hardware and software readiness, to insure high availability and quality operation is sustained during development as well as production manufacturing
- Graduating Senior or Junior in Electrical Engineering, Device Physics, Material Science, Semiconductor Process, Computer Engineering or other relevant engineering or physical science discipline is required
- Must have experience with Software Engineering
25
Smts Design Enablement Resume Examples & Samples
- Bachelor’s Degree + 8-10 years of experience
- Master's Degree + 7 years or PhD + 5 years
- Strong experience using the Cadence Design Environment
- Basic experience developing automation and scripting
- Experience developing parameterized cells (Pcell)
- Strong experience using SKILL programming language
- Experience using a GDS layout viewer
- Basic knowledge of semiconductor processing
26
Senior Eng Design Enablement Resume Examples & Samples
- To create and maintain testcases for Process Design Kit elements, and perform quality assurance checks to ensure quality deliveries to customers
- Reviewing and interpretation of Design Manual and Spice Model documents to QA Process Design Kit elements
- To investigate, support and review feedback from customers regarding PDK elements developed by the team
27
Smts Design Enablement Resume Examples & Samples
- Understanding ESD and latchup groundrules fully
- Understanding and modifying complete ESD and latchup tool flow
- Evaluating alternate tools for existing checks today, multiple vendors for same types of checks
- Master/PhD in Electrical Engineering
- 10-12 years of related experience
- Team player with good communication at all levels of the organization
- Global / regional exposure is an added advantage
28
Smts, Design Enablement Resume Examples & Samples
- Develop comprehensive technology training collateral to deliver to internal teams as well as customers
- Provide expert-to-expert customer interface on key PDK and flow topics
- The ability to work independently in an international team, to drive project definition, execution, and delivery is highly desirable
- At least 10 years of relevant work experience with an M.S. degree in Electrical Engineering or related field
- Strong EDA tool scripting and automation experience (TCL, Perl, Make)
- Ph.D. degree in Electrical Engineering or related field with 7 years of experience
- At least 5 years of experience in CAD organization
29
Pmts Design Enablement Resume Examples & Samples
- Scoping new enablement projects or project changes to support customer requirements
- Align customer needs and project schedule to design enablement development schedules for
- BSEE with 10 years of experience
- Domestic or international travel approximately 15-20%
- Fluency in both Chinese ( Mandarin ) and English Language
- Strong communication and negotiation skills with the ability to project risk
- International team player who is comfortable in multiple environments and cultures
30
Smts Design Enablement Resume Examples & Samples
- B.S.in Engineering with 8 years of experience
- 2 years’ experience with design tools and/or physical layout
- 2 years’ experience of direct customer facing, support role
- Fluency in both Chinese ( Mandarin ) and English Language - written & verbal
- Good project management skills
31
Design Enablement Intern Resume Examples & Samples
- MSc enrolled in accredited Electrical Eng, Computer Eng or Physics (degree program, ie Electrical Engineering or Electrical and Computer Engineering program)
- PhD enrolled in accredited Electrical Engineering, Computer Engineering or Physics (degree program)
- Ability to create or view physical layout and run DRC using Mentor Graphics or Cadence tools
32
MTS Design Enablement Resume Examples & Samples
- Work closely with Fab test, product engineering, diagnostics and failure analysis organizations to drive optimal DFT recommendation to the foundry customers
- BSEE, Electrical Engineering, Computer Engineering, or other relevant engineering discipline
- MS or PhD, Computer/Electrical Engineering or other relevant engineering discipline
- Understanding of test engineering, etst equipment (ATE) and test
33
Principal Eng Design Enablement Resume Examples & Samples
- Looking for a candidate with 15+ years of solid hands-on experience and leadershp in Physical Design
- Should have good experience leading chip level implementation from Netlist to GDSII physical design implementation flow at block level (2M plus) as well as top level, including floorplanning, placement, signal & clock routing, static timing analysis, power analysis and Physical Verification & extraction using industry standard tools
- Should also have good experience handling multi-million hierarchical designs, along with the sign-off checks, EM/IR, XTalk and DFM
- Candidate should be knowledgeable in PERL/TCL/AWK/Shell scripting. Candidates who are self-driven and has worked in a global team environment with ownership of blocks or chips level PD with successful track record of taping out complex 32/28/16/14 nm SOCs will be preferred
- Should have excellent problem solving skills, written & oral communication , teaming & inter-personal skills with experience in providing mentorship to junior engineers, reviewing designs and providing technical guidance
34
MTS Design Enablement Resume Examples & Samples
- This position is required in the team which is responsible for defining and implementing low power architecture, implementation/verification techniques and required tool/flow/methodology for ASIC designs
- Candidate need to be able to understand IP/Library and have hands-on experience in implementing/verifying low power in designs, in the area of Synthesis, physical implementation and signoff
- Additionally, Candidate need to be well versed with the design methodologies and tools to be able to define/automate them and enable new methodologies in the domain of Low Power
- Candidate will be responsible for development/refinement of advanced solutions in the area of power refinement and management
- Candidate will play a key role in development or defining micro-architecture strategies for low power, improved power integrity, performance and area. Candidate will be required to work with cross-functional teams to devise and validate the low power implementation
35
MTS Design Enablement Resume Examples & Samples
- This position is required in the team which is responsible for implementing DFT / Test on complex IP and SOC for ASIC designs
- Candidate need to be able to understand DFT/Test architecture
- Candidate need to have hands-on experience in implementing DFT/Test in designs in the area of DFT Synthesis, verification and pattern generation/simulation
- Additionally, Candidate need to be well versed with the design methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test
- Candidate will be responsible to implement DFT/Test on IP/SoC design for DFT Synthesis, verification and pattern generation/simulation
- Candidate will work with worldwide design teams and research teams to influence the DFT/Test roadmap
36
Design Enablement Co-op Engineer Resume Examples & Samples
- Design and simulate benchmark circuits in RF technologies
- Characterize and analyze fabricated benchmark circuits
- Provide technology and PDK feedback based on the circuit design
- Education – Graduating Senior or Junior in Electrical Engineering specialized in RF/mmwave
37
Design Enablement Intern Resume Examples & Samples
- Develop engineering scripts for automation. Convert various scripts (ksh, perl, etc) from an afs (Andrew File System) to a unix based file system . Some scripts will require the addition of new features and support for new data structures
- Run simulations and compare circuit performance, capacitance, and resistance across various vendor tools
- In pursuit of BS Degree in Electrical or Computer Engineering, or other related discipline from an accredited College and or University and currently enrolled as a Junior or Senior
- In pursuit of MS Degree in Electrical or Computer Engineering, or other related discipline from an accredited College and or University
- Self-motivated, able to take ownership of assignments
- Design experience
- Experience with SQL (databases)
- Experience with Cadence Virtuoso or similar tool
- Programming skills
38
Smts Design Enablement Resume Examples & Samples
- PhD, Computer/Electrical Engineering or other relevant engineering discipline
- Design for Test experience and programming skill is desirable
- Have design customer interaction experience
39
Senior Eng Design Enablement Resume Examples & Samples
- Develop scripts and automated tools to improve the quality and cycle-time of Tapeouts
- Manage tapeout projects from pre-tape-in to Release to mask write. Collaborate with tapeout stakeholders to define
- BS/BTech + min 3 years of experience or MS/MTech with min 75% marks
- Experience in Unix/Linux environment including knowledge in shell scripting
40
Technology Design Enablement Engineer Resume Examples & Samples
- Candidate should have 5+ years of experience in process technology development or related areas
- Thorough understanding of deep sub-micron processes, device physics, process integration, IC design and test
- Design experience in advanced CMOS process is desired including strengths in transistor level circuit design
- Excellent data analytical, problem solving and communication skills
- People management skills and managerial experience is highly desired
- Ideal candidates will have prior experience in success of delivering new designs to production under a very aggressive schedule
- Self-motivated and schedule oriented is a big plus
41
Design Enablement Engineer Resume Examples & Samples
- Create benchmarks, proof of concept designs, and customer specific design examples through use of high level design techniques such as OpenCL and High Level Synthesis as needed
- Demonstrate how to port accelerators from GPU or other technology to FPGA by developing customer specific example designs
- Work with sales teams to understand sales objectives to ability to demonstrate solutions to customers
- BS in Computer Science, Electronics Engineering or related * 5 years of relevant industry experience FPGA, CPU, GPU, DSP, ASIC, or extensive digital design * Experience with the use of FPGA development tools (i.e. Quartus, ISE, Vivado, etc.) * Experience with OpenCL, or similar high level design language(s) * Experience, or knowledge, with FPGA hardware acceleration architecture *Willing to travel on occasion Additional Preferred Qualifications * MSEE, MSCS, or MS in Computer Engineering * Understanding of FPGA code optimization using parallelism, pipelining, memory management
42
Pmts Design Enablement Resume Examples & Samples
- Close interaction with analog and RF design team and require a good understanding of implementation implications of design choices
- Develop state-of-the art digital data-path and signal processing for Analog, RF and mmWave
- Analog and RF digital system specification, simulation, and performance evaluation
- Perform RTL and verification simulations to meet specifications
- Behavioral modeling for different RF, analog and digital blocks
- MS in Electrical Engineering or higher degree in Digital design or/and DSP
- Digital communications, signal processing, communication theory
- Experience with Digital or Discrete-time Signal Processing mainly for RF radios
- Experience with Low-power Interpolation and decimation filter design and implementation
- Design experience with Transmitter, Receiver and DPLL architectures
- Experience with 3GPP other relevant specifications
- Ability to work with early PDK (before production)
- Experience with digital signal processing tools
- Experience with lab characterization of digital & Mixed-Signal integrated circuits
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Design Enablement Engineer Resume Examples & Samples
- Create benchmarks, PoC, and customer specific design examples
- Demonstrate how to implement GPU/accelerator based designs in FPGA technology
- Demonstrate strong presentation, and communication, skills to present the capabilities of Intel’s product portfolio, and perform demonstrations of feasibility studies, and proofs of concept, in customer meetings and seminars
- BS in Electronics Engineering or related
- An internship, work experience, or educational projects that includes experience with FPGA, ASIC, ASSP, CPU, DSP, or digital design, including embedded system design (HW and SW)
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Design Enablement Intern Resume Examples & Samples
- Implement PPA analysis at both synthesis and PnR level
- Determine the optimal technology solution for specific design requirements
- In pursuit of BS Degree in Electrical Engineering, or related discipline from an accredited College and or University and currently enrolled as a Junior or Senior
- Basic scripting skills, such as Tcl, Python
- Strong data analysis skills
- Experience with Physical design, Synopsys or Cadence synthesis and route tools
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Pr Eng Design Enablement Resume Examples & Samples
- BS/BTech + min 6 years of experience or MS/MTech + min 3 years exp
- Experience in Perl
- Experience in DRC, OPC, or Mask Technology will be a plus
- Good proficiency in English (written and verbal)
46
Smts Design Enablement Resume Examples & Samples
- Able to perform physical quality assurance checks of RF model kits at the netlist level and in custom design environment to ensure error free PDK kits delivery to customers. Run customer’s RF testcases/netlists for model QA/de-bugging
- Create and update RF model kit/RF simulator qualification release and application notes
- Good understanding of the device physics of SOI and bulk CMOS RF transistors and the correlation of the process
- Min. Bachelor Degree in Electrical and Electronics or Microelectronics Engineering
- Software programming skills in UNIX, LINUX and Windows environment
- Expertise in RF circuit designs, layout implementation, testing and silicon validation with models
- Familiar or has worked on foundry’s PDK and usage for deep submicrometer and/or nanometer testchip tapeouts
- Good knowledge of SOI and bulk CMOS semiconductor processes for RF technologies on 12, 14, 22, 28, 40, 55, 65, 130 and
- 180nm nodes
- Effective communicator and good presenter
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Princ Eng Design Enablement Resume Examples & Samples
- Develop & maintain Exhaustive QA procedures for Library/IP Qualification with Customers as end users. Goal of IP Quality Team is to provide Bug Free Library/IP to customers
- Qualify and maintain AMS/PHY, other complex IP and keep its QA Records
- Work closely with the IP Vendor & Internal design Team to identify the Design kit issues
- Support for IP silicon validation and debugging failures
- Support additional requests from Field / Customer Support on IPs failing on customer side or if such information is needed to address the customer needs
48
Design Enablement Engineer Resume Examples & Samples
- Develop and support DFM decks utilizing pattern matching methodologies
- Design and implement new DFM techniques to enable 22nm, 14nm, 12nm, 7nm technology nodes and below
- BS Degree in Electrical Engineering, Computer Science, or related field
- Expertise in IC design for advanced technology nodes
- Working knowledge of Pattern Matching software and coding utilizing Mentor, Synopsys or Cadence software
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Design Enablement Software Resume Examples & Samples
- Devising the software architecture, in collaboration with the system architect and sales team,
- Specify, develop and validate embedded drivers, firmware and applications running on embedded processors in Intel PSG FPGA
- Specify, develop and validate drivers and applications running on host processors, connected to FPGA-based accelerators
- Designing software applications including GUI that showcase the power of FPGA based applications in an exciting and provoking manner
- Bachelor of Science in Software Engineering, Computer Science or related field-Hands on experience programming embedded systems in C/C++ with at least 5 years of experience developing drivers, firmware, applications
- Knowledge of and experience with the most common peripherals used in the embedded world PCIe, Ethernet, .
- Good knowledge of Linux operating system, as well as embedded OSes
- Experience in developing attractive user interfaces for PC based applications
- Proven track records of completed software commercial projects
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Fpga Design Enablement Engineer Resume Examples & Samples
- Work with sales teams to demonstrate FPGA technology to customers in emerging markets
- Create benchmarks, PoC, and customer specific design examples, demonstrated on suitable hardware
- Work with customer designs to show how they can be optimized, close timing and be successfully debugged
- Strong presentation, and communication, skills to demonstrate feasibility studies, and proofs of concept, in customer meetings and seminars
- 5 years of industry experience or equivalent in FPGA, ASIC, ASSP, CPU, or DSP, or extensive digital design
- Extensive knowledge of FPGA Development, Simulation and Verification tools both from Intel PSG and 3rd Party EDA Vendors
- Strong understanding of VHDL, Verilog System Verilog, and TCL scripting
- Willing to travel
- MSEE, MSCS, or MS in Computer Engineering
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Senior Eng Design Enablement Resume Examples & Samples
- Education - BS/MS degree in Computer Science, Engineering or a related subject
- BS/BTech + 3yrs industry experience or MS/MTech + 1yrs
- Proven software development experience in PHP and MVC design patterns
- Strong understanding of JavaScript and JQuery
- Good understanding of JavaScript frameworks such as AngularJS, ReactJS, or BackboneJS
- Good understanding of asynchronous request handling and AJAX
- Demonstrable knowledge of web technologies including HTML, CSS, etc
- Good knowledge of relational databases, and integration of multiple data sources
- Passion for best design and coding practices
- Knowledge of authentication/authorization between multiple systems, servers, and environments
- Proficient understanding of code versioning tools, such as Git
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Smts Design Enablement Resume Examples & Samples
- Lead collaboration with design rule, lithography, etch and modeling engineers in cross-functional team environments to determine optimal computational solutions
- Initiate ,lead and deliver proactive and preventive technical solutions avoiding potential development roadblocks
- Research, apply and continually improve industry and company best practices surrounding OPC development
- Provide mentoring to less experienced engineers in the OPC development function
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Smts Pathfinding Design Enablement Resume Examples & Samples
- Bachelor's degree in Engineering, Science or Computer Science
- At least 5 years of EDA, CAD or enablement experience
- Experienced using a physical layout editor / viewer
- DRC coding experience
- Demonstrated strong capability with scripting languages (eg Python, Perl, TCL, shell, etc.)
- Skilled in the use of multiple EDA tools in the Design Enablement and Mask Dataprep Flows
- Ability to identify tooling technical challenges from disruptive pathfinding technologies and translate into actionable projects
- Ability to understand technical issues from collaboration with subject matter experts
- Ability to communicate complex technical topics crisply to non-subject matter experts at all levels in the organization
- Capable to develop engineering PDK components such as DRC, LVS or PEX
- Ability to collaborate in a geographically diverse organization with research, development, CAD, enablement and ground rule teams
- Ability to work independently with strong written and oral communication skills.Fluency in English Language - written & verbal - Fluent
- Master's or PhD degree in Engineering, Science or Computer Science
- At least 7 years EDA, CAD, PDK development or design enablement experience
- Experience with LVS and DRC verification tools (Synopsys / Cadence / Mentor Graphics)
- Experience with parasitic extraction and timing assertions
- Experience with process emulators (Coventor / Synopsys SPX)
- Working experience using Cadence SKILL programming language or equivalent
- At least 1 year experience in semiconductor design, digital or mixed signal
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MTS Design Enablement Resume Examples & Samples
- Characterize and analyze AC and DC electrical data representing transistor characteristics of semiconductor active devices
- Build and develop device models based on hardware extraction, simulation, or targets for leading edge CMOS logic technologies
- Conduct model quality checks on compact models and resolve any quality issues
- Write testplans for characterizing electrical data representing CMOS technologies
- Write software programs to analyze electrical data representing CMOS technologies
- Generate statistical models
- Conduct model to hardware checking and integration in Design System model checking
- Design new test structures to enable the device model process. Do design, verification through electrical data
- Expertise in semiconductor device physics
- PhD in Electrical Engineering or Physics
- At least 2 years’ experience in applied application of semiconductor device physics
- At least 1 year experience in applied application of compact model generation
- Experience with compact modeling and knowledge of SPICE level simulators such as Hspice or Spectre
- Experience with Verilog-A
- Strong programming skills (e.g. Perl, Python)
55
Senior Eng Design Enablement Resume Examples & Samples
- Development of BSIM4, BSIMSOI, BSIM-CMG, BSIM-IMG and PSP Spice models for advanced technology nodes
- Support of GLOBALFOUNDRIES external customers with occasional travel to their sites on as needed basis
- SRAM modeling, cell level simulations and supporting infrastructure development
- Development of models for Local Layout effects, Noise, RF and Statistical Modeling
- Collaboration with EDA companies on the simulator issues and support to meet world class customer needs
- Masters in Electrical Engineering or Computer Engineering or Physics, or related engineering field with 1-2 years research work experience in semiconductor devices
- PhD in EE, Computer Engineering or Physics or related engineering field with 3 years research experience in CMOS device physics and IC design
- Excellent ability to meet tight deadlines, commitments and deliver customer requirements
56
Principal Eng Design Enablement Resume Examples & Samples
- FET statistical modeling for advanced technology nodes
- Working closely with Device engineers on the technology development,
- Occasional reliability modeling support
- Up to 2 years of industry experience and experience in CMOS device physics, or Advanced Semiconductor Manufacturing process and circuit design
- PhD in EE or Physics with up to 3 yrs experience is preferred
- Expertise in CMOS device physics and IC design
- Fluent with Perl, Python and shell scripts
- Hands on experience with LVS/PEX extraction
- Good knowledge on circuit analysis such as delay chain, ring oscillator
- Strong Leadership skills as well as good aptitude for analytical problem-solving, and a keen orientation for details
- Good relationship building skills
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Eng Design Enablement Resume Examples & Samples
- Work with R&D and Fab Process Integration & Module teams to help define advanced test chip for new technology development
- Provide custom layout design for I/O Cell, Analog Macro and Memory Layout Design
- Understand test structures/IP/macro fully; be able to provide technical support/guidance to other engineers
- New Test Pattern Design & Develop new/sophisticated EDA code for automation test structure generation
- Generate methodologies for continuous improvement
- To ensure successfully accomplish of the responsibilities and goals
58
Smts Design Enablement Resume Examples & Samples
- Develop BSIM4, BSIMSOI, PSP, BSIM-CMG and BSIM-IMG Spice models for advanced technology nodes, with emphasis on FET layout effects and statistical modeling
- Develop SPICE infrastructure/methodologies with emphasis on FET layout effects and statistical modeling
- Develop test structures for SPICE model characterization
- Collect relevant data and perform statistical analyses for Model Hardware Correlation
- Define relevant UPL (Unified parameter list) targets, and simulate them with an advanced node PDK flow
- Work with Device teams on technology definition, development, targets, and benchmarking
- Work with PDK teams to provide world-class design enablement solutions
- Work with IP Development teams and GLOBALFOUNDRIES customers to deliver world-class designs
- Support Product Line Management and Field Engineering teams
- Collaborate with EDA companies on simulator issues and support to meet world-class customer needs
- Masters in Electrical Engineering or Physics
- 8+ years industry expertise in Advanced CMOS device physics,
- PhD in EE or Physics with 8+ yrs experience is preferred
- Experience with FinFET or Fully-Depleted SOI CMOS device physics
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Princ Eng Design Enablement Resume Examples & Samples
- Works with internal design enablement, process integration, unit process module, OPC, and tapeout teams to define and develop device truth table, mask generation rules/algorithms required for DRC/LVS/reticle procurement by advanced technologies
- Creates and maintains specification documentation while ensuring rigorous change process procedures are adhered to
- Validates mask generation solution, creating test suites as necessary, and providing guidance/approval for mask release
- Actively participates in interlocking activities with other organizations to ensure successful tapeout
- Education – B.S. in Electrical Engineering, Materials Science, Solid State Physics, or other relevant engineering or physical science discipline
- Experience – 3+ years of semiconductor device or process integration experience; Good understanding of device truth table, mask generation rule/Boolean; Solid understanding of semiconductor device physics, process integration, design rule definitions; Able to use design tools to view layout design and run DRC checks for design rule evaluations
- Travel – (% of travel required) typically < 5%
- Physical Capacity Demands – none
- M.S. or Ph.D. in Electrical Engineering, Materials Science, Solid State Physics, or other relevant engineering or physical science discipline
- Strong interpersonal skills and ability to work effectively with different culture and organization across various locations
- Familiar with advanced semiconductor manufacturing processes (28nm generation and smaller)
- Experience in OPC and/or mask data preparation
- Experience with design rule calculation and rule margin analysis
- Knowledge and experience in physical layout design
- Coding proficiency
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Smts Design Enablement Resume Examples & Samples
- Unified Spice model Loop Closure and UPL methodology/flow development/enhancement
- Automated flow development/enhancement for quick model optimization
- Spice library QA and integration with PDK
- Efficient data management (compatibility and sharing)
- Spice model web application development and support
- Uniform Setup for model extraction/QA/silicon correlation/release flows
- Collaborate with EDA companies on the simulator support/issues
- Masters in Electrical Engineering, Physics or Computer Engineering
- Industry experience and expertise in infrastructure development and support for semiconductor modeling and design
- Excellent software skills: Python, Perl, Java scripts, web programing and shell scripts
- Expertise with SPICE level simulators such as HSPICE, SPECTRE
- Strong written and oral communication skills in English
- PhD in EE or Physics with 6+ yrs experience is preferred
- Good understanding of all PDK components linked closely to Spice models
- Great team player with excellent coordination skills
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MTS Design Enablement Resume Examples & Samples
- Develop process design kit (PDK) components, specifically decks for design rule checking (DRC)
- Validate PDK component implementation with automated and manual quality checks
- Bachelor’s Degree in Electrical Engineering, Microelectronics, or equivalent
- Minimum of 8 years of work experience in semiconductor and/or EDA industries
- Working knowledge of software test techniques
- Experience with Advanced DRC topics (e.g. Antenna checks, ESD, Latchup, Decomposition techniques ...etc.)
- Familiarity with Cadence Virtuoso tools and SKILL language is preferred
- Familiarity with GLOBALFOUNDRIES process technology is preferred
- Self-motivated, resourceful, shows initiative and needs minimum supervision
- Solid understanding of semiconductor processes in advanced technology nodes (28nm and below)
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Smts Design Enablement Resume Examples & Samples
- At least 5 years of relevant experience in Semiconductor IP/Library Design (standard cells, memories, I/O’s, Analog Blocks, PHY/Serdes), preferably as a former design or applications engineer
- Experience with qualification and integration of various IPs into ASIC/SoC
- Experience with either Front or Back-end (Including HSPICE) tools from Synopsys and Cadence
- A deep understanding of IP design, ASIC Design Flow and integration related issues
- Excellent verbal and written communication skills. Proven customer facing skills
- Experience with creating various applications materials
- Bachelor’s degree or equivalent in Electronics Engineering, Computer Science, or closely related field. MSEE is preferred
63
Smts Design Enablement Resume Examples & Samples
- Working closely with lab engineers on the device characterization (DC/AC/Transient/RF), Data analysis. Model Hardware Correlation
- Working closely with worldwide Device engineers on the technology development
- Close interaction and support of Product Line Management, Field Engineering teams
- Technology Benchmarking for advanced technology nodes
- 6+ years of industry experience and expertise in CMOS device physics, Advanced Semiconductor Manufacturing process and IC design
- Expertise with SPICE level simulators such as HSPICE, SPECTRE, or ELDO
- Understanding of design flows, methodologies and variation margins
- Past Management experience
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Senior Eng Design Enablement Resume Examples & Samples
- 2-3 years academic research work
- 3+ years academic research work
- CMOS device physics and IC design
- Good relationship building skills and strong written and oral communication skills
65
MTS Design Enablement Resume Examples & Samples
- Spec, Scope, create and maintain dummy generation enablement for PDK’s
- Support dummy generation for internal and external Tape Out
- Education – BS in Electrical Engineering, Computer Science, Chemical Engineering, or Material Science
- Experience – 3+ years of work experience in semiconductor or EDA industry
- Travel – (% of travel required) Less than 10%
- Language Fluency – English
- Physical Capacity Demands – Fit for normal office work
- Good understanding of physical synthesis in VLSI design
- Solid understanding of VLSI process technology
- Outstanding communication skills – both written and oral; demonstrated ability to communicate at various levels within an organization
66
Pmts Design Enablement Resume Examples & Samples
- B.S. in Electrical Engineering or Engineering related field
- 10+ years’ experience with design tools and/or physical layout
- Fluency in English Language - written & verbal
- M.S. or PhD in Electrical Engineering or equivalent Engineering field
67
MTS Design Enablement Resume Examples & Samples
- Developing test structures to performed coverage, accuracy and inter tool run result consistency
- Developing scripts to automate process independent test structure development and result analysis
- Developing PDK consistency checks as well as verifying Analog Reference Flow and PDK compatibility
- Strong programing knowledge and knowledge of Python and Cadence SKILL programing languages is a plus
- BS in EE, CE or equivalent degree with 5 years of experience
- Strong programing knowledge and knowledge of Python and Cadence SKILL programing languages
- MS in EE, CE or equivalent degree with 3 years of experience
68
MTS Design Enablement Resume Examples & Samples
- Development of SPICE modeling infrastructure and methodologies
- Modeling Test structure development for characterization and Modeling
- 7+ years of industry experience and expertise in CMOS device modeling, advanced semiconductor manufacturing process or circuit design
69
MTS Design Enablement Resume Examples & Samples
- Initiate, lead and deliver proactive and preventive technical solutions avoiding potential development roadblocks
- Initiate and lead technical teams in root cause analysis of printing and yield limiting hotspots using proven tools
- Lead and participate in cross-functional semiconductor development projects
- Education - Masters Degree
- Experience – 5+ years semiconductor or similar engineering or software development
- Travel – up to 25%
- Masters or PhD in Electronics, Engineering, Computer Science, Mathematics, Physics or related disciplines with 5+ years of experience in semiconductor development
- In depth understanding of semiconductor development and OPC or similar Electronic Design Automation (EDA) knowledge
- Demonstrated expertise in scripting and computer languages such as C++, Python, PERL, TCL, shell and others
- Expert knowledge of lithography, RET, OPC, mask data preparation, and design rules, and demonstrated experience in a technology development environment
- Demonstrated experience with and knowledge of the following skills: analysis of statistical data, resolution enhancement techniques, modeling, simulation, programming especially in a cluster environment, numerical methods and techniques
- Expert knowledge and demonstrated application of lean-sigma and the various tools used in a lean-sigma environment
- Demonstrated leadership of and ability to collaborate with upstream and downstream development teams
70
Pmts, Design Enablement Resume Examples & Samples
- Develop front-to-back design flows for Analog-Mixed signal applications. Flow would cover from circuit schematic to final layout, considering the steps of pre-layout simulations, layout implementation & automation, DRC, LVS, PEX, post-layout simulation & EMIR analysis
- Collaborate closely with EDA vendors, foundry technologists, PDK and design teams to define, implement, customize, and qualify design flows
- Develop methodologies for flow & interoperability qualification of PDK components
- Very good understanding of process technology and AMS design,and analysis EDA tools and flows
- Deep hands-on experience with custom implementation tools and flows - Cadence Virtuoso/ADE; Mentor Calibre (DRC, LVS, PERC); PEX (at least one of Synopsys StarRC, Cadence Quantus, Mentor Calibre); EMIR (at least one of Cadence Voltus-FI, Ansys Totem) and simulation for advanced technologies
- At least 15 years of relevant work experience with an M.S. degree in Electrical Engineering or related field
- Ph.D. degree in Electrical Engineering or related field
- At least 15+ years of experience in CAD organization
- Strong communication skills within a global team and the ability to define and execute projects independently
71
Senior Eng Design Enablement Resume Examples & Samples
- Master or Phd Degree in in Electrical and Electronics or Microelectronics Engineering
- Minimum 1-2 years of device modeling experience. Strong understanding of RF aspects of CMOS, Passive Devices, and characterization of devices are highly essential
- Experience in developing RF model or circuit design in RF SOI and Bulk Technologies
72
Senior Eng Design Enablement Resume Examples & Samples
- Perform incoming IP QA against a predefined QA checklist and meeting committed cycle time. This includes verify the IP DK and Silicon deliverables against contract. To issue certificate of approval when QA has passed & certificate of Non-conformance when QA has failed
- To qualify IP merge kit to support customer tape-out
- To maintain & timely update IP information in IP database and IP Catalog
- Define comprehensive test case for IP qualification & IP regression
- Support scripting and automation to improve work efficiency
- Continuous improvement in QA methodology and test case suite to ensure high quality of IP to support customer engagement & tape-out
73
Pmts Design Enablement Resume Examples & Samples
- RF benchmark circuits design expertise. Implementation of RF layouts for silicon fabrication. Perform RF models loop closure using the silicon-based benchmark circuits
- Able to perform physical quality assurance checks of RF model kits at the netlist level and in custom design environment to ensure error free PDK kits delivery to customers. Run customer’s RF testcases/netlists for model QA/debugging
- Perform qualification of 3rd party RF simulators and scoreboard compilation
- Good understanding of the device physics of SOI and bulk CMOS RF transistors and the correlation of the process technologies to the transistors’ RF performance. The key Figure-of-Merits of interest include Ft, Fmax, 1/f noise, HF noise, IIP3, OIP3, P1dB etc
- Familiar with DC/AC/RF/noise/large-signal characterization and model extraction of SOI RF transistors using BSIM-SOI and PSP-SOI model architectures in SPECTRE and HSPICE model formats. Familiar with DC/AC/RF/noise/large-signal RF characterization and model extraction of bulk CMOS RF transistors using BSIM4.x, BSIM6 and PSP model architectures in SPECTRE and HSPICE model formats
74
Circuit Design & Enablement Engineer Resume Examples & Samples
- Enabling digital and analog circuit design and development with EDA tools
- Schematic Entry of electrical designs using Cadence tools
- Layout Entry of physical designs using Cadence tools
- Schematic and Layout extraction / netlist generation
- Circuit simulation for verification of design
- Physical and electrical circuit design rule generation (Verilog, Lef, cdl, gds, .lib, etc)
- Education – BSEE or BSCE
- Experience – At least 8 years of experience with any transistor level EDA design, simulation, and analysis tools
- MSEE or MSCE
- At least 10 years of experience with Cadence transistor level EDA design, simulation, and analysis tools
- Circuit design EDA Tool experience across legacy and advance technology nodes
75
Pmts Design Enablement Resume Examples & Samples
- Familiar and able to perform DC/AC/RF/noise/large-signal characterization and model extraction of SOI RF transistors using BSIM-IMG, BSIM-SOI and PSP-SOI model architectures in SPECTRE and HSPICE model formats
- Familiar and able to perform DC/AC/RF/noise/large-signal RF characterization and model extraction of bulk CMOS RF transistors using BSIM4.x, BSIM6 and PSP model architectures in SPECTRE and HSPICE model formats
- Able to design and coordinate RF active GSG layouts and device matrices planning for RF modeling testchip development
- Create and maintain testcases for GLOBALFOUNDRIES RF transistor models integration into PDK kits, perform simulations and physical quality assurance checks to ensure error free PDK kits delivery to customers. Run customer’s RF transistor testcases/netlists for model QA/de-bugging
- RF transistor scribestreets implementation for statistical RF data monitoring and correlation to RF transistor models variability
- In-depth experience of high frequency and thermal noise characterization and modeling. Ability to operate and maintain Focus Microwave electromechanical high frequency noise tuner-based characterization system
- Good knowledge of SOI and bulk CMOS semiconductor processes for RF technologies on 14, 22, 28, 40, 55, 65, 130 and 180nm nodes
