SOC Design Engineer Resume Samples

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DQ
D Quitzon
Douglas
Quitzon
30238 Nikita Tunnel
Philadelphia
PA
+1 (555) 961 7879
30238 Nikita Tunnel
Philadelphia
PA
Phone
p +1 (555) 961 7879
Experience Experience
Dallas, TX
SOC Design Engineer
Dallas, TX
Bosco-Pagac
Dallas, TX
SOC Design Engineer
  • Power and performance analysis, design verification, simulation model development of various SoC blocks
  • Work with diverse team of algorithm engineers, software engineers and ASIC engineers to develop SoC solutions
  • Work with DV team for DV failure triage, and provide RTL fix
  • Lab electrical validation of leading edge SerDes IOs, and network SOC's
  • Validating the fullchip power behavior of next generation chipset designs by developing testplans, tests content, coverage points or test tools
  • Oversees definition, design, verification, and documentation for SoC System on a Chip and SiP System in Package development
  • Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results
Los Angeles, CA
AMP SoC Design Engineer
Los Angeles, CA
Cronin-Zulauf
Los Angeles, CA
AMP SoC Design Engineer
  • Work with the Microarchitecture team to develop specifications for multicore SoC AMP products
  • Work with other design and verification teams to jointly develop complex SoC and platform solutions
  • Work in close partnership with Systems engineering teams and lead customers, to drive leading edge products
  • Drive advanced implementation methodologies and apply them efficiently in the daily workflow
  • Apply technical leadership, coordinate and supervise subcontractors or off-site teams who provide design and verification solutions for our products
  • Design complex multi-core SoCs for Automotive applications as well as complex digital subsystems
  • Deep expert knowledge of SoC design
present
San Francisco, CA
Lead SoC Design Engineer
San Francisco, CA
Hickle-Beier
present
San Francisco, CA
Lead SoC Design Engineer
present
  • OSOC IP integration and RTL Design for performance, low area, and low power
  • Proven track record of high performance designs in high volume production for low power applications
  • ODesign interfacing to PD for floorplanning and timing closure
  • Proven track record of RTL design and timing closure on large complex designs
  • OUPF flow for defining power intent of chips with multiple power domains
  • OASIC design flow and netlist flow checks – Lint, CDC, Logical Equivalence
  • Familiarity with DFT and backend related methodology and tools is a plus
Education Education
Bachelor’s Degree in Electrical Engineering
Bachelor’s Degree in Electrical Engineering
Liberty University
Bachelor’s Degree in Electrical Engineering
Skills Skills
  • Good Design knowledge, good basics of ASIC flow, good digital fundamentals . Strong in Verilog/SV, VCS/Verdi etc.
  • Strong problem solving ability, good communication skills
  • Self-Motivated, disciplined, professional and good work ethics
  • Exposure to Synthesis flow, Should have good scripting skills – perl, tcl
  • Be able to develop the actual RTL in System Verilog base on the uArch specification
  • Ability to work Individually and as a Team
  • Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing
  • Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs
  • The RTL should be able to synthesize efficiently that meets our timing, area, and power constraint from uArch Specification
  • Good documentation and communication skills
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15 SOC Design Engineer resume templates

1

SOC Design Engineer Resume Examples & Samples

  • Assisting design unit owner in Register Transfer Level (RTL) model functional validation
  • Using CAD tool extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions
  • Verifying the circuit behavior against the original simulation model and first silicon
2

Senior Asic SoC Design Engineer Resume Examples & Samples

  • Managing multi-site design projects for customer products and partnering with external design service firms to meet project goals
  • Working with internal and external technical teams to manage the development of implementation methodology, design collateral requirements and a production ASIC design flow
  • Managing the implementation of physical designs, such as pre-layout synthesis/optimization, floor planning, power-grid and clock tree designs, timing budgeting, place and route, RC-extraction and integration
  • Managing the verification of physical designs, such as functional equivalency, timing/performance, noise, layout rules, reliability and power
  • Planning, reviewing and ensuring resources are in place for activities in engineering function to meet schedules, standards, and cost
  • Identifying and analyzing problems, plans, tasks, and solutions
  • Setting strategic direction and building strong technical organization
  • Cultivating innovation and creativity environment
  • High levels of motivation and ability to deal with ambiguity
  • Ability to work with external technology companies for collaborative development of SOCs
  • Ability to work in a tight schedule environment
  • Knowledge of CPU and chip set architectures would be an added advantage
3

SOC Design Engineer Resume Examples & Samples

  • Circuit IP characterization and SOC integration
  • SOC clock and power design and validation
  • High speed IO digital logic and firmware control
  • Lab electrical validation of leading edge SerDes IOs, and network SOC's
  • Verilog RTL Logic design preferred
  • Experience with high speed IO, interconnects, and lab equipment
  • Candidate should have strong written and verbal communication skills
4

Low Power SoC Design Engineer Resume Examples & Samples

  • Strong problem solving skills, good customer orientation, and effective communication skills are key for the position
  • Mininum of 3 months experience in digital and analog circuit design, CMOS design, and scripting languages
  • Experience with SPICE simulators
  • Good knowledge of UNIX/LINUX
  • Good knowledge of Excel
  • Scripting languages: Tcl, Perl, and C
5

SOC Design Engineer Resume Examples & Samples

  • Bachelor's or Master's degree in Electrical/Computer Engineering or Computer Science
  • System debug skills
  • Understanding of software and/or hardware validation techniques
  • Assembly programming skills
  • Understanding of simulation techniques and hardware modeling
  • Hardware and software debug skills
6

SOC Design Engineer Resume Examples & Samples

  • Previous engineering work experience as an intern or full-time engineer
  • Experience in circuit design, characterization, and physical integration
  • Technical understanding of industry IC/SOC design tools
  • IO design and signal integrity analysis exposure
  • Using lab equipment for high speed Electrical characterization and validation
7

Senior SoC Design Engineer Resume Examples & Samples

  • Should possess a Bachelor's degree in Computer or Electrical Engineering with 10+ years, or a Master's degree in Computer or Electrical Engineering with 8+ years of of relevant experience in IC Design, verification and integration of internal/3rd party IPs into SoC products
  • Experience in all phases of the silicon product development lifecycle, from concept and high-level specification to silicon to production
  • Experience working in a matrixed organization, preferably with teams in other time zones and countries
  • Good working knowledge of high speed I/O protocols such as PCIe/SATA/USBx, Ethernet and SoC fabrics
  • Good knowledge of System Verilog, Lint tools, CDC, Synthesis, Formal Verification, OVM/UVM
  • Experience in Synopsys Coretools, VCS/Modelsim, Synopsys Design Compiler, Spyglass
  • Experience in Unified Power Format (UPF) methodology (implementation and simulation) is highly desirable
  • Knowledgeable in OOP (Object-Oriented Programming) and scripting languages such as C/C++, Perl, TCL, Java
  • Knowledge in HVM, DFX, Scan, JTAG, VISA is an added advantage
8

SOC Design Engineer Resume Examples & Samples

  • Must have a BS in Electrical Engineering, Computer Engineering, Computer Science
  • 4+ years of hardware physical design experience
  • 3+ years of expertise with physical and logical design tools such as Synopsys flows and methodology (ICCDP, Design Compiler, IC compiler, ICC, Primetime tools)
  • 3+ years of experience with physical design convergence, integration, and tape out of multiple ICs
  • of scripting skills using Perl and Tcl
9

Senior RLS SoC Design Engineer Resume Examples & Samples

  • Block level floorplanning, taking into account timing and area budgets; bottoms-up pin/port placement based on analysis of design; RF EBB placement; etc
  • Netlist generation, including logic synthesis, constraints, timing analysis and equivalence checking (FEV)
  • Place-and-Route (APR) using Synopsys ICC
  • Timing verification using Synopsys PrimeTime, noise/RV/ERC/power analysis, etc
  • Physical verification of the layout (LVS, DRC)
  • Highly motivated technical expert with good communication and presentation skills
  • Ability to multi-task and flexibility to work in global environment
  • Strong expertise in the RTL2GDSII (RLS, synthesis) flow development or design implementation in leading process technologies (28nm or below)
  • Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure, UPF based power methodology, etc
  • Working experience with tools like ICC, Primetime etc used in the RTL2GDSII implementation
  • Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools
10

Senior.soc Design Engineer Resume Examples & Samples

  • This includes resolving issues in RTL2GDS flow like, Logic synthesis, FEV, Block level floor-planning, multi-power domain complexities, Place & Route, clock tre synthesis complexities like balancing the clocks between multiple clocks, LVS & DRC cleanup, timing closure , Electrical Rule Fixes and Quality fixes
  • Candidate will also be responsible to be part of methodology development in critical design issues, troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention
  • Good understanding on synthesis, PnR, Timing closure , FEV
  • Experience with UNIX, Perl and TCL also desired in order to implement usable, flexible C-shell/ Perl/ TCL programs that automate tool/flow methodologies
  • Must have hands-on experience with industry tools in one or more of these areas. Familiarity with Design Compiler, ICC and timing convergence tools would be added plus
11

HW SoC Design Engineer Resume Examples & Samples

  • BSEE/MSEE and at least 10+ years’ experience with the following
  • Experience with High speed, Low Power Designs
  • Experience with CPU & IP Integration, such as PCIe and/or DDR Memory Controllers, DMAs, High Speed Interfaces, SOC System Bus Design
  • Experience with SOC Bus Protocols such as ARM AMBA; Bus Interfaces (AXI, AHB, APB), and/or OCP
  • Experience in authoring Micro-Architecture/Design Specifications and Converting them to Design
  • Perform Front End Integration tasks including: Lint, CDC, Synthesis, and ECO
  • Experience in DFT Methodologies and Formal Verification Tools
  • Experienced in Synthesis Flows with Standard Libraries and different Process Nodes (e.g., 28nm, 22nm, …)
  • Familiarity with Scripting Languages like Gmake/Perl/Tcl/Python
  • Experience in Low Power Design and Implementation Technique, knowledge of UPF and Power Intent Verification
  • Experience with Power and Clock Management Designs
12

SOC Design Engineer Resume Examples & Samples

  • Synthesis and Static Timing Analysis (STA) with Design Compiler and Primetime
  • Random constrained, coverage driven verification
  • Object Oriented Analysis and Design
  • Embedded Firmware
13

SOC Design Engineer Resume Examples & Samples

  • RTL to block level design execution and methodology which includes logic synthesis, auto-place and route, extraction, low power design, static timing analysis and convergence, logical equivalence verification, reliability convergence, layout verification of tape-out databases
  • Fullchip design verification on ASIC design projects which include fullchip static timing analysis and closure, Reliability verification and layout convergence
  • Define and support signoff methodology for all areas related to Performance Verification (PV) including timing analysis, power estimation and noise glitch analysis using PrimeTime and Tempus tool suite
  • Interface heavily with ASIC/SOC design teams to understand the design requirements and resolve flows and methodology issues related to synthesis and place&route
  • Work directly with external customers and help them achieve optimal results with Intel technology
  • Demonstrate experience and hands-on practical knowledge with standard-cell based VLSI design methodology and relevant Synopsys or Cadence EDA tools
  • Demonstrate strong analytical and problem solving skills through relevant experiences with ASIC/SOC design convergence
  • Hands-on expertise and experience in sign-off timing analysis on advanced nodes. Excellent understanding of cross-talk, on-chip variation and STA based ECO capabilities
  • Excellent communication and leadership skills are a strong plus
  • Demonstrate experience in scripting with Unix shell, Perl and TCL
14

SoC Design Engineer Full Chip Timing Resume Examples & Samples

  • Full-chip timing lead for signoff verification of physical designs in various modes and PVT corners for timing/performance, noise, reliability and power
  • Collaboration with the Methodology and Design Automation teams on timing verification flows, signoff modes & corners, Design margins
  • Design & Architecture understanding, Interaction with FE/DFT/Verification teams
  • Timing constraints development including IO budgeting for partitions, Understanding synchronous & asynchronous paths, Clocking & Clock domain crossing issues
  • Understanding and debugging extraction and STA issues
  • Drive the designs to timing closure in a hands-on capacity, interacting/supporting synthesis and APR team during timing closure cycle, timing ECOs, Timing signoff & quality checks
  • Support the post-Si team with debug of any issues seen on Silicon. Work with the post-Si team to analyze and correlate STA data with Silicon timing
15

SOC Design Engineer Resume Examples & Samples

  • Strong and proven technical leadership skills. Motivated and self-directed
  • Excellent knowledge of ASIC design and verification methodology
  • Proven track record of delivering complex ASIC/SoC successfully
16

SOC Design Engineer Resume Examples & Samples

  • Learning of IP interoperability (in System Verilog, Verilog or other Hardware description language)
  • Validating the fullchip power behavior of next generation chipset designs by developing testplans, tests content, coverage points or test tools
  • Modeling power behavior including performing power simulations and power optimization
17

SOC Design Engineer Resume Examples & Samples

  • BS in Computer or Electrical Engineering or related, or 15 years of experience in design/verification of complex protocols
  • Experience with hardware design and validation
  • Experience with ASIC/FPGA
  • Experience with standard interface protocols
  • MSEE/MSCS or related
  • Experience with Ethernet MAC and PHY IP
  • Experience with static timing analysis
  • Experience with hardware validation
18

Principal SoC Design Engineer Resume Examples & Samples

  • MSEE or PhD in Electrical Engineering, Computer Engineering with 10+ years industry experience
  • Leadership experience in multiple SOC/ASIC/FPGA projects
  • Proven track record of successful silicon, introduced to market
  • Deep knowledge of Verilog RTL design and simulation environments
  • Expertise on STA, with preferred experience in PrimeTime
  • Ability to lead cross functional silicon bring-up team for SOC projects
  • Strongly desired experience in multiple of the following
19

SOC Design Engineer Resume Examples & Samples

  • 6+ months of experience in digital logic design and/or verification
  • 6+ months of experience in hardware description language VHDL or Verilog and/or System Verilog
  • 6+ months of experience in verification language System Verilog
  • 6+ months of experience Logic simulation tools such as Modelsim and VCS
  • 6+ months of experience in Synthesis and Static Timing Analysis STA with Design Compiler and Primetime
  • 6+ months of experience in Random constrained, coverage driven verification
  • 6+ months of experience in FPGA design and verification
  • 6+ months of experience in Industry standard verification methodologies like OVM, VMM, eRM and UVM
  • 6+ months of experience in Object Oriented Analysis and Design
  • 6+ months of experience in Embedded Firmware
20

SOC Design Engineer Resume Examples & Samples

  • BS in Computer or Electrical Engineering or equivalent
  • Experience with Hardware Design and Validation
  • MS in Computer or Electrical Engineering
  • Experience with Static timing analysis
  • Experience with Hardware validation
21

SOC Design Engineer Resume Examples & Samples

  • 10+ years of experience in Verilog RTL Logic Design of mult-million gate ASICs
  • 10+ years of experience with PCIe End Points
  • Experience with PCIe Root Complex
  • Familiarity with Automated Front End Design Flows
  • Experience with bring up and Lab Debug
22

SOC Design Engineer Intern Resume Examples & Samples

  • Functional RTL simulations / simulator
  • System Verilog / OOP - Unix & scripting languages
  • Problem solving / debug skills
  • Good attention to detail and communication skills
23

SOC Design Engineer Resume Examples & Samples

  • Bachelor’s Degree (Masters Preferred) in Electronic Engineering or Computer Engineering with 4+ years of related experience
  • Strong verification background, including system-verilog-based environment development, test plan and test development, simulation-based debug
  • Experience with simulation and debug tools, including VCS simulator and Verdi
  • Strong programming skills, languages including System Verilog, C++, Python, Perl, and assembly language
  • Emulation experience
24

SOC Design Engineer Resume Examples & Samples

  • Experience in all phases of logic development lifecycle from high-level specification to tape-out and production
  • Knowledge of DFX - Scan, JTAG, VISA, etc
  • Experience using 1 or more: Synopsys Coretools, VCS/Modelsim, Synopsys Design Compiler, Spyglass, Lint and one or more scripting languages
  • Experience using 1 or more of the following languages: Verilog, System Verilog, Perl, Tcl, Python C/C++
  • Candidates should have design/ uArch experience (DFX preferred)
  • Knowledge/experience in Unified Power Format (UPF) methodology (implementation and simulation) and OVM/UVM are desirable
  • Candidates should also have experience with RTL simulators, VCS preferred
  • Good interpersonal skills and the ability to work in a highly cooperative team environment across several time zones are also desirable
25

IP / SOC Design Engineer Resume Examples & Samples

  • Defining and documenting IP or SOC microarchitecture based on requirements documents (industry standards, product requirements)
  • Implementing SOC and IP logic functions meeting requirements specification and passing all NXP standard quality checks
  • Managing IP deliveries, chip bill-of-materials and releases versus functional, milestone and schedule requirements
  • Clocking and reset architecture, especially in complex multiple-clock and reset domain designs
  • Physical design planning (area, timing, power), handling of timing constraints, pipelining, timing closure, place-and-route implications of design tradeoffs
  • Integration of large complex blocks from multiple sources including 3rd party vendors, including performing signoff lint and clock crossing checks
  • One or more specialty functions of the SOC, such as high-speed serial protocols, memory controllers, ARM cores, AMBA interconnect, and packet processing
  • Minimum BSEE/BSCE/BSCS. MSEE/MSCE/MSCS a plus with 10+ years of experience
  • This position requires a high level of SOC design skills (design documentation, Verilog RTL coding, synthesis, static and formal checkers, etc.)
  • Knowledge of ARM AMBA® protocols required
  • Other programming skills (SystemVerilog UVM, C/C++, Perl, TCL, etc.) a plus
  • Knowledge of high speed serial protocols (PCI Express, 10G or faster Ethernet) a plus
  • Verification skills (test planning, testcase development, coverage) a plus
26

SOC Design Engineer Resume Examples & Samples

  • Hardware description language (VHDL or Verilog and/or System Verilog)
  • High-level verification language (System Verilog* preferred)
  • PCIe, NVMe, SAS/SATA and Nonvolatile media (preferred)
27

SOC Design Engineer Resume Examples & Samples

  • Be able to develop the actual RTL in System Verilog base on the uArch specification
  • Review Timing Report from Structural design team, and work with uArch and SD team for timing closure
  • Work with DV team for DV failure triage, and provide RTL fix
  • 3+ years of experience in high performance ASSP logical design
  • 3+ years of experience and understanding of scripting language (Perf, Phython, make file, etc)
  • Experience in Clock Gating, Power Island, and Reset operation is a plus
28

SOC Design Engineer Resume Examples & Samples

  • Bachelor's degree or a Master's degree in Electrical Engineering, Computer Engineering or a related discipline
  • 6 months of experience in the following areas * Digital logic design and/or verification * Hardware description language VHDL or Verilog* and/or System Verilog* * High-level verification language System Verilog* preferred * Logic simulation tools such as Modelsim and VCS * PCIe, NVMe, SAS/SATA and Nonvolatile media
  • Synthesis and Static Timing Analysis STA with Design Compiler and Primetime
  • Industry standard verification methodologies like OVM, VMM, eRM and UVM UVM preferred
29

Senior SoC Design Engineer Resume Examples & Samples

  • Oversees definition, design, verification, and documentation for SoC (System on a Chip) development
  • Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs
  • Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing
  • Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development
  • Verilog RTL Logic Design
  • RTL IP Integration
  • Full chip RTL Integration and release process for multi-million gates SoCs/ASICs
  • Perform full chip Front End Integration tasks including: IP and subsystem integration, Lint, CDC, Synthesis, equivalence checking
  • Experience with at least one of the following: processor integration, system bus integration, DDR controllers, or PCIe
  • Familiarity with automated front end design flows
  • Proficient with scripting Languages like Gmake/Perl/Tcl/Python
30

SOC Design Engineer Resume Examples & Samples

  • Strong knowledge of ASIC/SoC design methodology, digital logic design
  • Experience in coding with System Verilog, Verilog and scripting languages like Perl, Python, tcl, etc
  • Familiar with block-level and hierarchical chip-level synthesis flows
31

SoC Design Engineer Validation Resume Examples & Samples

  • Experience in design verification of ASIC and FPGA projects at block and chip levels
  • Own and be responsible of pre-tapeout quality for digital SOC modules
  • Familiar with UVM and be able to develop testbench, drivers, sequences and checkers, monitors, scoreboards to achieve functional coverage
  • Be able to collaborate with design team to debug and root cause issues
  • Experience working with PCIe, AMBA AXI3/4 protocols is desirable
  • Experience with scripting languages like Perl, Python, etc. is desirable
32

SOC Design Engineer Resume Examples & Samples

  • Perform logic design, structural design using APR flows
  • Perform all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power, noise and RV to create a design database that is ready for manufacturing
  • Work with logic designers, TFM team and mask design communities to influence solutions and design convergence
  • Develops solutions to problems utilizing formal education and judgement
33

SOC Design Engineer Resume Examples & Samples

  • Minimum Qualifications BS or MS degree in Electrical or Computer Engineering or related fields
  • At least 10 years of logic design experience e.g., spec definition, RTL coding in Verilog or SystemVerilog, verification, synthesis, and timing analysis etc
  • 6+ years of hands on experience with integration and verification of ARM IP's e.g., CPU, GPU, CoreSight, AXI/ACE and APB bus protocols etc
  • Expert knowledge of industry standard SoC design tools and flows.Strong debug skills at IP and SoC levels and ability to work closely with validation engineers to help drive higher design quality
  • Scripting abilities perl/tcl.Experience in silicon debug either on ATE or in system
  • Strong written/verbal communication skills.Experience in successfully influencing and collaborating with teams in distributed locations
  • Knowledge of hardware interaction with firmware
  • Prior experience in leading a logic design team
  • Prior experience in leading post-silicon efforts debug, validation etc
34

SOC Design Engineer Resume Examples & Samples

  • Hardware description language VHDL or Verilog and/or System Verilog
  • High-level verification language
  • PCIe, NVMe, SAS/SATA and Nonvolatile media
35

SOC Design Engineer Resume Examples & Samples

  • Micro-architecture, writing block-level specifications, logic design, functional verification, synthesis, static timing analysis STA and support of post-silicon validation
  • Firmware, Digital logic design and/or verification
  • VHDL, Verilog, SystemVerilog, Java and/or C/C++
  • Object Oriented Analysis and Design - Embedded Firmware
36

SOC Design Engineer Resume Examples & Samples

  • The suitable candidate must be pursuing Bachelor's degree of Science in Computer Science, Computer Engineering, or Electrical Engineering
  • The candidate must have unrestricted right to work in Canada without requiring sponsorship
  • 6 months experience with Firmware, Digital logic design and/or verification
  • 6 months experience with VHDL, Verilog, SystemVerilog, Java and/or C/C++
  • 6 months experience with logic simulation tools such as Modelsim and VCS
  • 6 months experience with synthesis and Static Timing Analysis STA with Design Compiler and Primetime
  • 6 months experience with random constrained, coverage driven verification
  • 6 months experience with industry standard verification methodologies like OVM, VMM, eRM and UVM UVM preferred
  • 6 months experience with object Oriented Analysis and Design
  • 6 months experience with embedded Firmware
37

SOC Design Engineer Resume Examples & Samples

  • Block-level floor planning
  • Logic synthesis of design blocks -Formal Equivalence Verification FEV
  • Auto Place-and-Route APR using Synopsys ICC tools
  • Timing verification using Synopsys PrimeTime as well as Intel tools
  • Physical verification
  • Layout vs. Schematic LVS, Design Rule Checks DRC, Electrical Rule Checks ERC, and Design for Manufacturability checks DFM
  • Assist in the preparation of the full-chip layout design database for introduction to manufacturing
  • Proven track record of executing challenging blocks from RTL synthesis to post-layout verification, owning blocks through synthesis APR, and solving timing/route/layout issues
  • Solid understanding of the Synopsys tool flow, including familiarity and experience with tools such as DC, ICC, PT, Caliber, and Conformal
  • Proficient in static timing analysis using Primetime
  • Experience with developing TCL/Perl utilities to solve issues and improve flow efficiency
  • Experience with low power implementations, with multiple power planes and power gating
  • Strong communication skills and the ability to work with cross-site teams to drive solutions, while meeting aggressive project schedules
38

SOC Design Engineer Resume Examples & Samples

  • Must have a BS/MS in Electrical Engineering or equivalent
  • Minimum of 3 months experience with Hardware/RTL design and Timing analysis concepts
  • Minimum of 3 months experience with scripting languages such as Perl, Python and Tcl
  • This job does require an existing background in electronics, programmable logic devices, or hardware RTL design
39

SOC Design Engineer Resume Examples & Samples

  • Determines architecture design, logic design, and/or verification simulation/emulation based
  • Defines module interfaces/formats
  • Strong problem solving skills -
  • Experience with top level RTL integration
  • Experience with implementing and working with emulation platforms
40

SOC Design Engineer Resume Examples & Samples

  • Bachelor or Master of Science degree in Electrical Engineering or Computer Engineering and at least 2 years of related industry experience.Additional qualifications include
  • Demonstrate strong analytical and problem solving skills through relevant experiences with ASIC/SOC design convergence.Hands-on expertise and experience in sign-off timing analysis on advanced nodes
  • Excellent understanding of cross-talk, on-chip variation and STA based ECO
  • Demonstrate experience in scripting with Unix shell, Perl and TCL.Self-driven with ability to prioritize work and accomplish tasks quickly with good problem solving skills
41

SOC Design Engineer Resume Examples & Samples

  • Support the design of a new SoC architecture based on signal processing requirements
  • Work with diverse team of algorithm engineers, software engineers and ASIC engineers to develop SoC solutions
  • Select SoC IP for inclusion in the design
  • Propose and evaluate architectural options for performing required signal processing functions
  • Plan signal processing algorithmic deployment to SoC technologies
  • Candidate must have at least a 8+ years and a Bachelor's or Master's of Science degree in Computer or Electrical Engineering, Computer Science, or related degree
  • Experience in Computer Architecture and processor design
  • Experience doing System-on-a-Chip (SoC) design and analysis
  • Experience defining SoC interconnect solutions (ARM NIC, CCN, Arteris, Sonics, etc…)
  • Experience with processor selection and configuration (ARM A-53/57/72, Tensilica BBE64, …)
  • Experience developing use case models for verification test plans
  • Comfortable solving complex problems
  • Ability to work in intensive and changing environment
  • Self-motivating, excellent written and verbal communication skills and good interpersonal skills
  • Must have a US Citizenship and be eligible for a DoD security clearance
  • Experience designing an SoC based on DSP algorithmic requirements and planning algorithmic deployment to hardware and software
  • Experience with pre-silicon hardware, algorithm and software validation
  • Experience with fixed point algorithm design in ASIC DSP and in software design
  • Experience with algorithm optimization for hardware
  • Experience validating hardware architectures using emulation and TLM models
  • Experience developing signal processing algorithms and software
  • Experience with signal processing algorithm optimizations for software
  • Experience with digital filter design and implementation in hardware and software
  • Experience bringing up post-silicon SoC
  • Experience supporting software and hardware teams through implementation, verification and bringup
  • Experience developing anti-tamper solutions
42

SOC Design Engineer Resume Examples & Samples

  • BSEE or MSEE with experience in FPGA, ASIC or custom IC designs
  • Strong background in System Verilog, OVM/VMM/UVM and C/C++
  • Demonstrated ability to create and document verification plans
  • Experience with high-speed transceiver protocols including PCI Express and Ethernet is desirable
  • Experience with high-speed memory protocols including DDR3/4 and HBM2 is desirable
43

SOC Design Engineer Resume Examples & Samples

  • BS or MS Degree in Electrical Engineering, Computer Engineering, or related degrees,
  • 6+ years of experience in Digital design including RTL, Verilog/SystemVerilog with a specific focus in data-protection logic and subsystems,
  • Full working knowledge of AES, SHA and HMAC functions & how to implement them in hardware, and experience leading technical teams
  • Circuit design understanding of clocking, basic circuits, timing issues
  • Experience working on SSD Controllers
  • Experience with synthesis and timing closure
  • Protocols knowledge
  • Bus, storage and DDR Experience with low-power design techniques
  • Strong problem-solving debugging skills,
  • Solid verbal and written communication skills,
44

SOC Design Engineer Resume Examples & Samples

  • Must be pursuing a Bachelor's or Masters in Electrical Engineering, Computer Engineering, Computer Science or other science/engineering related field
  • At the BS level only, must have the unrestricted right to work in Canada without requiring sponsorship
  • Minimum of 3 months experience in the following areas
  • Synthesis and Static Timing Analysis STA with Design Compiler and Primetime
  • Random constrained, coverage driven verification
  • Industry standard verification methodologies like OVM, VMM, eRM and UVM UVM preferred
  • Object Oriented Analysis and Design-Embedded Firmware
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SOC Design Engineer Resume Examples & Samples

  • 6+ months of experience working with micro-architecture
  • 6+ months of experience writing block-level specifications
  • 6+ months of experience working with logic design, functional verification and synthesis
  • 6+ months of experience working with static timing analysis STA and support of post-silicon validation
  • 6+ months of experience working with Solid State Drive SSD controller ASICs
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SOC Design Engineer Resume Examples & Samples

  • In charge of firewall specification, and verilog RTL coding in collaboration with SoC architecture and Front End integration teams
  • Involvement in the complete SoC design and development cycle
  • Digital RTL design & verification in Verilog
  • Synthesis / timing analysis
  • Highly motivated, proactive and fast learner
  • Microsoft Office (or equivalent)
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SOC Design Engineer Resume Examples & Samples

  • Experience with low power methodology and work flow, either CPF or UPF based
  • Development of CAD flows for low power
  • Experience with ASIC design
  • Experience with ASIC verification
  • Knowledge of SystemVerilog
  • Knowledge of UVM
  • Good documentation and communication skills
  • Ability to work Individually and as a Team
  • Self-Motivated, disciplined, professional and good work ethics
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SOC Design Engineer Resume Examples & Samples

  • Bachelor or Master of Science degree in Electrical Engineering, Computer Engineering or any related field
  • 3 to 6 months experience in
  • Standard-cell based VLSI design methodology and relevant Synopsys or Cadence EDA tools
  • ASIC/SOC design convergence
  • Scripting with Unix shell, Perl and TCL.Self-driven
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Lead SoC Design Engineer Resume Examples & Samples

  • This position requires thorough knowledge of the ASIC design flow, FE and Design verification, synthesis, scripting and netlist generation. The ideal candidate will have the following background
  • Proven track record of high performance designs in high volume production for low power applications
  • Proven track record of RTL design and timing closure on large complex designs
  • Expertise in
  • OSOC IP integration and RTL Design for performance, low area, and low power
  • OFE production synthesis with DFT insertion
  • OASIC design flow and netlist flow checks – Lint, CDC, Logical Equivalence
  • OUPF flow for defining power intent of chips with multiple power domains
  • ODesign interfacing to PD for floorplanning and timing closure
  • Strong communication skills are a must as the candidate will interface with a lot of different groups within and outside the company
  • Self starter, highly motivated, highly organized, and schedule driven is a must
  • Familiarity with DFT and backend related methodology and tools is a plus
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SOC Design Engineer Resume Examples & Samples

  • Experience with top level RTL integration Experience with implementing and working with emulation
  • Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation
  • Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing
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SOC Design Engineer Resume Examples & Samples

  • Must be pursuing a Masters or Bacherlos degree in Computer Science, Computer Engineer, Electrical Engineer or other related field
  • Experience with ASIC design and verification
  • Knowledge of System Verilog
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AMP SoC Design Engineer Resume Examples & Samples

  • Design complex multi-core SoCs for Automotive applications as well as complex digital subsystems
  • Work with the Microarchitecture team to develop specifications for multicore SoC AMP products
  • Work with other design and verification teams to jointly develop complex SoC and platform solutions
  • Drive advanced implementation methodologies and apply them efficiently in the daily workflow
  • Apply technical leadership, coordinate and supervise subcontractors or off-site teams who provide design and verification solutions for our products
  • Work in close partnership with Systems engineering teams and lead customers, to drive leading edge products
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SOC Design Engineer Resume Examples & Samples

  • Micro-architecture
  • Writing block-level specifications
  • Synthesis, static timing analysis (STA)
  • Support of post-silicon validation
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SOC Design Engineer Resume Examples & Samples

  • RTL Design, Micro architecture definition, implementation and integration of SOC components
  • Power and performance analysis, design verification, simulation model development of various SoC blocks
  • Documentation of specifications, review product requirements and logic block diagrams, prototype construction and checkout
  • Collaborate closely with other SoC projects at various sites across Intel
  • Adept problem solver with good problem solving skills
  • Ability to quickly adapt to changing conditions
  • Initiative to continually expand your skill set
  • System Verilog/VHDL, RTL design, power performance analysis
  • Simulation using VCS/Model sim, Debug tools such as DVE, Verdi
  • Programming languages such as C/C++; Scripting ability in UNIX shell script, Perl, TCL, or Python