DFT Engineer Resume Samples

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E McCullough

Elizabeth

McCullough

347 Francesca Track

Houston

+1 (555) 198 2796

347 Francesca Track

Houston

Phone

p +1 (555) 198 2796

Experience Experience

Los Angeles, CA

DFT Engineer

Los Angeles, CA

Streich-Effertz

Los Angeles, CA

DFT Engineer

Development and implementation of DFT architecture
Work on global SOC projects in global DFT project teams
Drive DFT architecture and methodology development in joint collaboration with global DFT and architecture teams
Generation of high-quality test and debug patterns
Support silicon bring-up activities at remote test locations
Education: BSc. in Electrical Engineering or Computer engineering
Silicon bring-up, diagnosis and support for physical failure analysis

Chicago, IL

SOC DFT Engineer

Chicago, IL

Collins-Friesen

Chicago, IL

SOC DFT Engineer

Post silicon support to ensure successful bringup and enhance yield learning
ATPG patterns verification with gate level simulation
Memory BIST logic generation, implementation and verification
Scan/Jtag/boundary scan insertion and ATPG pattern generation
Test coverage and test cost reduction analysis
Implementation and verification of DFT architecture and features
Work in close collaboration with frontend, verification, backend and test engineering teams

present

New York, NY

Senior DFT Engineer

New York, NY

Nader and Sons

present

New York, NY

Senior DFT Engineer

present

Work in a cross functional team in Silicon characterization and correlation to pre-Silicon Performance and Power models of Tegra/CPU/GPU type SOCs
Work with RTL, custom digital/analog, verification and physical implementation teams during DFT implementation
Responsible for DFT design/flow improvements
Work with Cross Functional Global Teams to define and implement DfT
Developing high coverage, cost-effective DFT methods
Drive performance verification on all DFT structures
Work with STA engineer to define timing constraints for DfT modes

Education Education

Bachelor’s Degree in Computer

University of Massachusetts Amherst

Bachelor’s Degree in Computer

Skills Skills

13)Good communication skills in English, written and verbal
Perl, Tcl, Verilog, and Unix
Experience with multiply aspects of the following
- ATPG, Test Coverage, Hierarchical retargeting
- JTAG, BSDL
- Memory and Logic BIST
- DFT Logic generation, integration and physical hardening
- Knowledge/experience with ATPG / DFT tools: Tessent, System Verilog, RTL and SDF gate verilog simulation, Synthesis scan stitching, power and static timing analysis, etc
Semiconductor Testing
Energetic, self-motivated

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SOC DFT Engineer Resume Examples & Samples

3-5 years of industry experience in DFT domain
Strong understanding of Scan and ATPG fundamentals
Must have worked on at least 2~3 SOC
Should have worked in SOC SCAN with Mentor TK
Experience in design and verification of test control logic (TCU)
Should have expertise in pattern generation for different fault models, coverage analysis and improvement using Mentor Fastscan
Experience in gate level simulation; with and without timing
Should know Verilog/VHDL/Perl/TCL scripting

Mixed Signal DFT Engineer Resume Examples & Samples

Strong fundamental knowledge of DFT/DFD techniques
Strong fundamental knowledge on transistor level circuits with mixed signal/analog background
Experience in Logic Design, Verilog RTL, verification, and static timing analysis
Knowledge in fault modeling Stuck-at, Transition, Path Delay and other advanced DFT models
Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing
Experience with industry ATPG tools such as Synopsys Tetramax or Mentor Fastscan ATPG tools
Working knowledge in Perl preferred
Detail oriented with strong organizational, problem solving and communication skills

Senior DFT Engineer Resume Examples & Samples

Work in a cross functional team in Silicon characterization and correlation to pre-Silicon Performance and Power models of Tegra/CPU/GPU type SOCs
Responsible for generating path delay ATPG patterns for correlating speed paths with silicon
Running MBIST patterns on SRAM memories for silicon correlation/debug

Senior DFT Engineer Resume Examples & Samples

Planning at IP or fullchip level
Implementation and verification for MBIST
Implementation and verification for Scan/LBIST/ATPG
Design/verification for Clock/JTAG/Analog/DFT IP etc
Pattern generation, release and ATE bringup
Responsible for DFT design/flow improvements

SOC DFT Engineer Resume Examples & Samples

Implementation and verification of DFT architecture and features
Scan/Jtag/boundary scan insertion and ATPG pattern generation
Memory BIST logic generation, implementation and verification
ATPG patterns verification with gate level simulation
Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, … etc)
Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design

DFT Engineer Resume Examples & Samples

Implement SOC DFT functions including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
Participate in ATE bring-up and debug the DFT patterns on ATE
BS in EE & CS, with 0-2years’ experience
Hands on working experience on ASIC DFT design and verification
Familiar with ASIC design flow

MTS DFT Engineer Resume Examples & Samples

Perform verification on all DFT structures
Generate DFT related timing constraints and work with PD team for timing closure
Design and implement other DFX (debug, characterization, yield etc) logics
BS in EE & CS, with 5+ years’ experience
Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic
Good English hearing, speaking, reading and writing capabilities
LI-CO1

Senior DFT Engineer Resume Examples & Samples

Participate and drive SOC full Chip DFT feature and architecture definition
Responsible for DFT specification generation and review
Drive a team to implement SOC DFT functions including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
Drive performance verification on all DFT structures
Generate and verify DFT structural patterns and functional patterns
BS in EE & CS. MS preferred, with 10+ years experience
Familiar with entire ASIC design flow
Experience with micro processor design a big plus
LI-DM1

DFT Engineer Resume Examples & Samples

Degree in Electrical or Computer Engineering; MS with 2+ years' experience/ BS with 5+ years experience in RTL environments and/or silicon design/validation
Experience with RTL environments such as Verilog
5 years in RTL environments and /or silicon design
Extensive knowledge of the DFT concepts
Experience with Synopsys and/or Mentor ATPG tools
Knowledge of different fault models and structural methodologies for coverage
Experience with Scan Architectures, atpg validation and atpg silicon bringup
Experience supporting multiple design teams and understanding SOC design flows
Good perl, tcl Scripting skills
LI-USA-BH1

Senior Principal DFT Engineer Resume Examples & Samples

Assume the Technical Leadership role as a DFT Architect.prove existing design verification methodology, tools and flows
Development of DFT Test insertion, Verification and Implementation flows
Development of Full chip test ( ATE) Plan
Complete Architecture level responsibility of DFT
Areas of Test Expertise required
Involved in RMA debug and 8D
Work with functional teams to generate Functional tests to ensure adequate coverage
Fluent in STA & SDC’s

Cpu-dft Engineer Resume Examples & Samples

The ideal candidate will have 5+ years of DFT experience, leading DFT efforts for large processor and/or SOC designs
Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
Experience developing DFT specifications and driving DFT architecture and methods for designs
Knowledge of industry standards DFT and design tools
Solid Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon
Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG/1500 related issues
Experience with STA constraints development and analysis for DFT modes and SDF simulations
Ability to conduct experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data

DFT Engineer Resume Examples & Samples

3-7 year experience in DFT implementation and verification
Detailed knowledge on DFT concepts, scan-insertion, ATPG, MBIST and pattern simulation
In-depth knowledge and hands on experience in scan-insertion, test mode timing constraints definition, LEC
Good understanding of MBIST implementation and verification
Scripting/Automation Skills Perl, Python, Shell, Make file TCI Gate-Level Simulation and Debug 0-delay, timing annotated
In depth knowledge and hands on experience in ATPG, coverage analysis, Transition delay test coverage analysis
Should have excellent inter-personal and communication skills
Exposure to silicon bring up and silicon testing is a definite plus

Senior DFT Engineer Resume Examples & Samples

Degree in Electrical or Computer Engineering; MS with 7+ years experience/ BS with 9+ years experience in RTL environments and/or silicon design/validation
Experience with silicon design or validation
Experience with SCAN, ATPG, MEMBIST, Array test, DFT methodology
9+ years in RTL environments and /or silicon design

Senior DFT Engineer Resume Examples & Samples

Working with digital design and backend teams on DFT architecture/partitioning
Running RTL, gate, and gate with SDF simulations to confirm correct functionality of DFT logic
Generating ATPG vectors, bring-up and debug patterns, resolve test pattern and coverage issues, support test engineering and operations through qualification, burn-in, and production
Design DFT logic including inserting MBIST, boundary scan, scan, and at speed ATPG (Transition Delay Fault Testing)
Support failure analysis, fault isolation of pattern failures and silicon debug
Experience with silicon lab bring-up and silicon diagnostic
Familiar with Low power, multi-power domain and mixed-signal design
Hands-on experience with RTL coding and design
Familiar with physical design and ASIC design flow & methodology
Familiar with yield analysis and improvement

DFT Engineer Resume Examples & Samples

Knowledge of Verilog HDL and experience with simulators and waveform debugging tools
Expertise in industrial standards and practices in DFT, including JTAG, ATPG, MBIST and trade-offs between test quality and test time
Expertise in debugging ATPG patterns, MBIST setup/patterns, and JTAG/1500 related issues
Experience on analog IP tests or test setup (PLL, high speed IO, ADC/DAC, and so on) will be a big plus
Experience with front-end design methodology including STA, Formal Verification, Synthesis, Linting, CDC, and so on

Senior DFT Engineer Resume Examples & Samples

Implement modern DFT solutions for leading edge ICs on latest technology nodes
Work with RTL, custom digital/analog, verification and physical implementation teams during DFT implementation
Work with cross functional groups to verify DFT implementation pre tape-out
Drive successful bring-up of test features post tape-out
Add to the in-house expertise on DFT to consult with, educate, and train design staff members on DFT requirements on how to prepare new designs to work properly with Cavium DFT solutions
Proficiency in working with cross functional and cross site teams
Must have the ability to multi-task in a fast paced environment

DFT Engineer Resume Examples & Samples

1)Be familiar with Fault modeling : Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models
2)Be familiar with JTAG and I2C
3)Experience on timing constraints and Synopsys synthesis
4)Experience on Verilog RTL to support chip-level test mode pin-multiplexing and timing analysis
5)Experience of working together with production engineers on yield analysis/debugging and test time optimization
6)Be familiar with Scan insertion, Scan Compression, scan Simulation
7)Be familiar with MBIST. Experience on memory repair is a plus
8)Be familiar with Industry ATPG/MBIST tools(Mentor/Synopsys)
9)Be familiar with Lint(Spyglass), CDC(0-in) and formal check(Conformal LEC)
10)Has experience of debugging ATE patterns with ATE team
11)At least 4 years hands on experience with DFT flow
12)Excellent team and interpersonal skills
13)Good communication skills in English, written and verbal

DFT Engineer Resume Examples & Samples

Experienced in Synopsys DFT and synthesis tools
Experienced in Mentor DFT tools
Familiar with Boundary scan implementation
Familiar with simulation tools
Familiar with Linux environment, skilled in csh/perl/tcl scripts , experience of Makefile preferred
Familiar in Low Power design/test
Good English communication skills both in verbal and written

DFT Engineer Resume Examples & Samples

Verilog
System Verilog or Specman
ATPG tools
Static timing analysis
Gate-level simulations
Silicon test, familiarity with ATE

DFT Engineer Resume Examples & Samples

Development and implementation of DFT architecture
Design and verification of DFT logic and components
Generation of high-quality test and debug patterns
Static timing analysis of DFT modes
Silicon bring-up, diagnosis and support for physical failure analysis
Experienced engineers as well as fresh graduates will be considered for the job
BSc degree in Computer Engineering/Electrical Engineering
Related courses: Logic Design, Introduction to programming, Algorithms and Data structures
For graduates – 85+ grade average (grade sheets are required when submitting a resume)
Several years in a semiconductor company as a DFT engineer
Chip design, Verilog and System Verilog
Verification, UVM methodology
Scan insertion tools
Scripting (Perl/Tcl)
Familiarity with ATE
Energetic, self-motivated
Pro-active, oriented on execution
Attentive to details and quality

Senior DFT Engineer Resume Examples & Samples

You will work with IP & integration design teams to understand the design and functional-mode behaviors of the logic & circuits
You will become familiar with the DFT designs of past Intel products to leverage their best-known methods and learn from their silicon experiences
Take those learnings, feed it back into the centralized dft team and deliver it to the other teams who would also benefit from the solutions
You will assist in the RTL, schematic implementation, pre-silicon validation & post silicon debug of these DFT features
You will be expected to deliver high-quality documentation for consumption by the pre/post-silicon teams who will use the DFT features

DFT Engineer Resume Examples & Samples

Design, integrate and verify DFT solutions for complex multi-core SoCs and Mixed-Signal MCUs
Work on: Test control (test modes), Memory BIST, Scan (On-Chip Compression/At-speed Scan/Test-clocking), Boundary Scan, Analog Test Subsystem, Test Pin-Muxing, Logic BIST
Drive advanced ATPG methods to ensure highest quality
Drive DFT architecture and methodology development in joint collaboration with global DFT and architecture teams
Work on global SOC projects in global DFT project teams
Work in close collaboration with frontend, verification, backend and test engineering teams
Be responsible for the in-time delivery of DFT production pattern per our quality metrics
Ensure that Test/DFT requirements are correct and complete and manage traceability down to verification results
Support silicon bring-up activities at remote test locations
Experienced in latest DFT methodologies: Scan insertion, Scan compression, ATPG pattern generation, At-Speed test, test coverage analysis, fault models
Good knowledge of DFT architectures for complex SoCs (embedded CPU)
Expert knowledge in state of the art EDA tools for DFT, design and verification. (Mentor, Cadence, Synopsys)
Proven expertise to simulate and debug DFT pattern on RTL and Gate Level
Experience in working with international teams
Experience and willingness to support silicon bring-up and debug activities
Ability to work in a global project organization with project teams distributed internationally
Preferred Skills: Experience in Scan architecture, DFT clock generation, ATPG (stuck-at, at-speed, small delay defect, cell aware), LBIST
Good Knowledge of scripting languages (TCL, Perl) to support design automation is a plus
Knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion is a plus
Willingness for business related travel to international NXP sites
Excellent written and verbal communication skills in English

Senior DFT Engineer Resume Examples & Samples

Define DfT Strategy, Requirement Specification and Arch for Mixed Signal SOC
DfT verification by gate-level simulations
Work with Cross Functional Global Teams to define and implement DfT
Work with STA engineer to define timing constraints for DfT modes
Support Test engineer in silicon debug and pattern delivery for ATE
Atleast 10 years of DfT experience in the semiconductors industry
Experience in Analog DfT is a major plus
Experience in using Mentor DfT tools, Cadence RC and simulator tools
Experience in using version control tools like Design Sync
Be fluent with all common concepts of DfT and DfT tools
Bring in some unique DFT expertise ( Low Power ..)

DFT Engineer Resume Examples & Samples

Knowledge: Must have very sound knowledge on ATPG, Scan insertion, Memory testing, memory repair, JTAG and boundary scan
Job Complexity: Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise
Experience: Typically requires a minimum of 8 years of related experience. At this level, post-graduate coursework may be desirable

Senior DFT Engineer Resume Examples & Samples

ATPG and scan pattern verification
Scan compression and decompression logic integration
Scan design rule checking at RTL and gates
DFx control through 1149.1 (JTAG) and 1687 (IJTAG) structure
Logic simulation tools and flows for verifying DFx logic
Memory built-in self-repair logic and its integration
Memory BIST logic and its integration into design
A Bachelor's Degree in Electrical Engineering, Computer Engineering or related field; MS or PhD preferred
3+ years relevant hands experience with RTL/Gate level design analysis and static timing analysis
Knowledge of scripting languages (Python, TCL or Perl) for automating solutions
Deep understanding of Design for Test (DFT) structures is required
Demonstrated experience in scan based testing, Scan Compression, Memory BIST, Logic BIST, and Boundary Scan (JTAG 1149.1 and IJTAG 1687)
Prior knowledge of Mentor Graphics’ Tessent solutions, including scan compression/decompression technology is a plus
Good communication skills, self-motivation, and teamwork are a must

DFT Engineer Resume Examples & Samples

Require BSEE/MSEE with 8+ years relevant industrial experience
Require good knowledge in DFT architecture and various DFT solutions on multimillion-gates mix signal SoC designs
Require good knowledge of Scan-compression techniques, AC and DC scan with on die PLL clocks, Memory-BIST, JTAG and Boundary-Scan
Require experience in getting the DFT patterns to work in ATE tester
Require good script (Perl or Python) writing experience
Prefer backend synthesis, STA tools experience
Prefer good RTL design, verification experience in SoC development
Prefer multiple high volume production tapeout experience
Rrefer extensive experience in resolving production qualification issue, dealing with customer RMA
Prefer experience with high complexity mix signal SoC designs
Prefer familiar with low power methodology
Prefer familiar with low power methodolog

Senior DFT Engineer Resume Examples & Samples

SAF, TDF, OCC, Scan Compression, MBIST, BISR, Logic BIST, JTAG
Hierarchical DFT Design
DFT insertion and pattern generation
RTL, Gate, and timing back-annotated simulation
Proficiency with Mentor Tessent MemBIST and TestKompress Tool
ASIC bring-up at ATE and bench test environment
Script (TCL, Perl, etc) development
Contribute to the continuous development of our DFT methodology
BSEE or equivalent with 5+ years DFT experience
Solid understanding of full ASIC design flow
Ability to multi-task, set priorities, leads, and works in a strong team environment
Positive, self-motivated and excited to learn new skills, tools, IP, and design flows
Relevant experience with ASIC physical design and timing closure
Static Timing Analysis and SDC generation
RTL Synthesis
Formal Verification
Knowledge of Verilog coding
Knowledge of ARM, High Speed SerDes, DDR, PCIE, NANDPHY

Senior DFT Engineer Resume Examples & Samples

Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs
Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, 1149.1 JTAG and IJTAG
Assist in Diagnosis and Yield enhancement through product lifecycle
BSc/MSc Electrical & Electronics Engineering with relevant logic design/test background
3-5 years’ work experience as a DFT engineer
Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
Proficient in logic design using Verilog and experience in synthesis and STA
Experience in developing test benches and simulation in RTL/GATE/SDF environments
Good communication skill and works well in a group environment that spans across continents
Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay), scan compression. Knowledge of MBIST is a plus
Knowledge of FPGA synthesis and design flow is a plus
Perl, shell scripting skills is a must

Senior DFT Engineer Resume Examples & Samples

Test cost
Test quality
Development and re-use of low consumption & low area test IPs
Cope with aggressive schedule and improve time to market
RTL coding and verification
Familiar with all aspects of implementation and verification of IEEE standards design
Familiar with all aspects of implementation and verification of memory BIST design
Familiar with ARM processor architecture
Familiar with all aspects of implementation and verification of scan design
Gate level verification
Test pattern generation
General silicon debug knowledge
ATPG tools (Mentor / Synopsys / Cadence)
Simulation tools (Cadence / Mentor / Synopsys)
Environment: Unix / DesignSync, SVN / Makefile / Perl
Scripting / programming capabilities (C, ASM, CSH, PERL…)
Real team player
Clear reporting
Ability to work within a challenging environment / schedules in a fairly manner