Staff Verification Engineer Job Description
Staff verification engineer
provides and present evidence and results of Functional safety analysis and level of compliance to ISO 26262 standard.
Staff Verification Engineer Duties & Responsibilities
To write an effective staff verification engineer job description, begin by listing detailed duties, responsibilities and expectations. We have included staff verification engineer job description templates that you can modify and use.
Sample responsibilities for this position include:
Use high level language concepts (Object oriented, UVM/OVM/VMM etc) to develop extendable environment
Build testbench components such as test and sequence libraries, monitors, models and BFMs by applying objected oriented programming verification techniques following UVM methodology
Develop UVM test bench components for SoC/block level verification
Develop and debug tests in UVM/C/C++
Designing, implementing and verifying high performance, low power parts of IoT IP in Verilog RTL
Develop verification testbench components for chip/module level using System Verilog, C & Perl
Define and execute detailed verification plan from spec working with architects, designers, system engineers
Write tests, automate regression scripts and regression environment
Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout
Debug tests, run gate level simulations at unit/sdf delays
Staff Verification Engineer Qualifications
Qualifications for a job description may include education, certification, and experience.
Licensing or Certifications for Staff Verification Engineer
List any licenses or certifications required by the position: ARM
Education for Staff Verification Engineer
Typically a job would require a certain level of education.
Employers hiring for the staff verification engineer job most commonly would prefer for their future employee to have a relevant degree such as Bachelor's and Master's Degree in Computer Science, Electrical Engineering, Computer Engineering, Engineering, Science, Electronics, Design, Electronic Engineering, Technical, Information Systems
Skills for Staff Verification Engineer
Desired skills for staff verification engineer include:
C/C++
UVM
Assembly language
Python
Cshell
ISO 26262
SOC components
Cache coherence and bus protocols
Cadence Incisive
Creating assertions
Desired experience for staff verification engineer includes:
Excellent understanding on software testing methodology
As a member of an industry leading project, implement verification/validation software tool for a high-end 64 bit super scalar micro-processor
Develop modules that will be used in a Random Instruction test-generator
Will be responsible for developing interesting algorithms that can improve the test generation efficiency and generate test-cases for maximal design coverage
Will be responsible for profiling the software design to figure out bottlenecks in the design and improve the code
Work with a team of DV engineers in development of various test cases
Staff Verification Engineer Examples
1
Staff Verification Engineer Job Description
Job Description Example
Our innovative and growing company is hiring for a staff verification engineer. Thank you in advance for taking a look at the list of responsibilities and qualifications. We look forward to reviewing your resume.
Responsibilities for staff verification engineer
- Use high-level language concepts (Object-oriented, UVM/OVM etc) to develop extendable environment
- Develop and maintain verification environment in SystemVerilog, VMM and UVM
- Develop automated/scripted design flows for the above mentioned development processes
- Participate in FPGA/silicon debug and analysis
- Work with high-speed, low power digital circuit designs from definition to implementation
- Verification of critical high speed, low power digital designs at IP and System level using both coverage driven random and directed testing techniques formal verification
- Own or be involved in all aspects of the verification flow from initial test planning to coverage and sign-off closure
- Lookout, evaluate and deploy new verification technologies
- Interact with architecture and design teams to identify verification requirements
- Architect test benches and create test plan documentation
Qualifications for staff verification engineer
- Candidate should have strong background in developing applications using C++/C
- Candidate needs to have a very good background in algorithms
- Candidate should have a background in assembly programming (x86, sparc, mips, arm), preferably ARM
- Minimum 8 years of work-experience in relevant areas as mentioned above
- Good knowledge in CPU architecture and verification/validation concepts
- Preferably candidate has an understanding of SVN, Git, GitHub or similar tools
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Staff Verification Engineer Job Description
Job Description Example
Our company is growing rapidly and is looking to fill the role of staff verification engineer. Please review the list of responsibilities and qualifications. While this is our ideal list, we will consider candidates that do not necessarily have all of the qualifications, but have sufficient experience and talent.
Responsibilities for staff verification engineer
- To interact closely with members of our other modelling teams to ensure compatibility of work
- Develop testbenches and verification IP
- Regression debug support, and other flow/infrastructure development
- You will implement highly complex SoC level verification environments, including stimulus and checking modules, for design products
- Definition and implementation of digital verification processes and infrastructure
- Architecting the verification strategy and plans for IP
- Represent the verification activities of the relevant projects, both internally and externally
- Review of subcontractors proposed test plans and Test Readiness Review (TRR) material
- Witness of tests performed by subcontractors
- Writing test procedures and preparing TRR material for natural and induced environmental testing
Qualifications for staff verification engineer
- Familiar with ARM, TI composing studios with solid knowledge on task sequence and modular architecture with lean management of firmware memory and processing resources
- OSystems using communication systems/protocols such as 802.3, PCIe, USB3, 802.11, ARM and their low power modes and system effect
- OFormal verification with abstraction model for end-to-end checking
- OLow power verification methodologies and quality measurements
- ODebug methodology
- Well-versed in the use of hardware verification languages SystemVerilog or Specman ‘e’
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Staff Verification Engineer Job Description
Job Description Example
Our growing company is looking for a staff verification engineer. Please review the list of responsibilities and qualifications. While this is our ideal list, we will consider candidates that do not necessarily have all of the qualifications, but have sufficient experience and talent.
Responsibilities for staff verification engineer
- Providing management with summary status of numerous test events
- Supporting the system requirements team in development of requirements
- Exposure to design and gate level simulations is a plus
- Independently model analog circuits and systems in Verilog
- Characterize and create timing models for the analog circuits
- Communicate regularly with the design and verification teams across the corporation
- Read and understand engineering documents for analog blocks and systems
- Perform digital and mixed analog/digital co-simulations to qualify the models developed
- Perform analog/digital co-simulations to verify mixed signal designs
- Mentor and coach junior design engineers, if and when required
Qualifications for staff verification engineer
- Verilog development of stubs and test-benches
- Expertise in function pipelining/partition, advanced logic design, system integration and simulation, verification and validation, failure analysis and debugging, design verification, quality-of-result optimization, engineering workspace/workflow functional or design verification flows/tools and closure/signoff
- Proficiency in personal skills including communication, presentation, adjudication, negotiation, compromise, agreeability, and inspiration, leadership to enable and escalate team members
- Exposure in computing security architecture, parallel computing architecture, hardware reliability architecture, system application use cases, system application integration and programming, system level debugging, benchmarking, and profiling
- Understand architecture specifications, verification strategy and compliance product
- Able to script and automate as needed
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Staff Verification Engineer Job Description
Job Description Example
Our growing company is hiring for a staff verification engineer. We appreciate you taking the time to review the list of qualifications and to apply for the position. If you don’t fill all of the qualifications, you may still be considered depending on your level of experience.
Responsibilities for staff verification engineer
- Occasional travel to Canada to gather project requirements
- Chip-level mixed-signal verification by integration of analog, digital and mixed-signal IP blocks at top-level for DDR4/DDR5 Memory applications
- Interface with design teams, methodology and CAD groups
- Define and execute a detailed verification plan from spec working with architects, designers, system engineers
- Debug tests, run gate level simulations
- Participate in silicon debug and analysis
- To technically support other engineers
- Defining and implementing the validation testplan
- Validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools
- Technically leading a team of validation engineers to achieve validation goals
Qualifications for staff verification engineer
- Btech/B.S
- Strong understanding of basic computer architecture and latest advances in the area of Multicores, Virtualization
- Power Management knowledge is a real plus
- ATPG and DFT knowledge is a plus
- BS EE, CE or CS
- Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required
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Staff Verification Engineer Job Description
Job Description Example
Our growing company is looking for a staff verification engineer. Please review the list of responsibilities and qualifications. While this is our ideal list, we will consider candidates that do not necessarily have all of the qualifications, but have sufficient experience and talent.
Responsibilities for staff verification engineer
- The Staff Systems Verification Engineer will be responsible for defining, designing, and executing system verification activities throughout all phases of the product development process for cellular analysis systems for research and clinical applications
- The Staff Verification Engineer will lead, provide technical supervision, and guiding senior-level engineering personnel
- The Staff Systems Verification Engineer applies engineering and technical problem solving expertise to the hands-on application of and performance measurement of flow cytometry systems
- The Staff Systems Verification Engineer will use good judgment in leading projects or initiatives of complex scope and/or direct teams of 10 or more contributors
- In addition, the Staff Systems Verification Engineer will engage in hardware/software integration testing, performance characterization, requirements analysis, test design, test execution, defect and customer complaint root cause investigations, and risk and hazard analysis
- He/she may be called upon to represent the voice of the customer to product developers, and assist with translating the customer needs to product requirements, specifications, and test methods to ensure needs are met
- Work with analog and mixed signal designers to create test benches for functional and timing verification under the supervision of a team manager
- Perform post-layout timing verification for analog and mixed-signal IPs using analog CAD tools
- Generate and validate various models including timing models (dotlibs)
- Work with external vendors in getting some of these done
Qualifications for staff verification engineer
- Excellent debugging skills in both SW and ASIC hardware
- Must be good in building verification environments preferably using the verification subset of high level languages like System Verilog (OVM, VMM), Specman, C/PLI
- Must be proficient in Verilog (System Verilog preferred)
- Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus
- Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy
- Good understanding of latest formal verification techniques, assertions, OOP etc is a plus