Layout Design Job Description

Layout Design Job Description

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Layout design provides guidance for: Market Specification, Functional Specification, Design Verification, Design Validation, Test Method Validation, Failure Mode Effects Analyses, and Design Reviews.

Layout Design Duties & Responsibilities

To write an effective layout design job description, begin by listing detailed duties, responsibilities and expectations. We have included layout design job description templates that you can modify and use.

Sample responsibilities for this position include:

Assist with tight tape-out schedules if needed
Physical design (layout) of analog and mixed-signal cells
Interface with design engineers to find optimal physical design solutions to complex analog/mixed-signal circuit designs
Work with RTL designer on testplan to achieve high code coverage and functional coverage
Build up simulation model
Test development and debugging
Work with RTL designer on testplan to achieve high code coverage and functional converage
Testcase development and debugging
Leverage existing test bench infrastructure develop new components for performance verification
Work with RTL designer on DUT verification

Layout Design Qualifications

Qualifications for a job description may include education, certification, and experience.

Licensing or Certifications for Layout Design

List any licenses or certifications required by the position: CID, IPC, IP

Education for Layout Design

Typically a job would require a certain level of education.

Employers hiring for the layout design job most commonly would prefer for their future employee to have a relevant degree such as Master's and Bachelor's Degree in Computer Engineering, Electrical Engineering, Design, Engineering, Computer Science, Electronics Engineering, Electronics, Science, Communication, Associates

Skills for Layout Design

Desired skills for layout design include:

Defining architecture
Micro-architecture
RTL design and functional verification
Entire design process from Design specification
Synthesis
Post-Si debug
Tape-out
Physical Design
Timing closure
Datapath compilers

Desired experience for layout design includes:

Proficiency coding with Verilog, simulating with NCSIM or VCS, & synthesizing with Synopsys DC or Cadence RC
Understanding OCV, DFM, DFY
Hands on experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools
Should have participated in a minimum of 5 fullchip tapeouts
BS degree or MS required
BSEE/BSCompE with 5+ years of relevant computer industry experience -or

Layout Design Examples

1

Layout Design Job Description

Job Description Example
Our company is looking for a layout design. Please review the list of responsibilities and qualifications. While this is our ideal list, we will consider candidates that do not necessarily have all of the qualifications, but have sufficient experience and talent.
Responsibilities for layout design
  • Perform fully-customized test structure layouts for pixel designs and verification
  • Clean database by using physical verification tools such as DRC, LVS and ANT
  • Develop test document for different test structure designs
  • Monitor electrical test parameters and debug issues, if any
  • Assist in the performance of product development activities, which includes drawing board layout
  • Assist in the interpretation and implementation of customer specifications and documentation requirements
  • Assist in the application of engineering principle knowledge to conduct routine analyses and/or tests pertaining to the development of new designs, methods, materials or processes
  • Assist in conducting engineering studies
  • Verification (DRC, LVS, ERC) and debug using the latest CAD tools
  • Chip-level assembly, optimization and verification
Qualifications for layout design
  • Quantifying power and performance improvement in popular benchmark and game applications (like 3D Mark, Firestrike, Battleman, ) with state-of-art modeling methodology
  • Feedback and driving key architectural decisions such as cache size, clock frequency, chip level power domain partition
  • Knowledge in SoC performance analysis like bandwidth, latency
  • Familiar with Verilog HDL, Tcl, Shell, Perl programming
  • Familiar with popular EDA tools
  • Knowledge of UPF/CPF-based low power design/flow is a plus
2

Layout Design Job Description

Job Description Example
Our company is looking for a layout design. If you are looking for an exciting place to work, please take a look at the list of qualifications below.
Responsibilities for layout design
  • Analysis power integrity with Apache/Totem
  • Establish/maintain version control system/software
  • Setup design automation with C-shell, Skill, Perl
  • Operate as part of worldwide team to develop and maintain design methodology
  • Individual contributor in the design team to create innovative high voltage gate driver ICs
  • Timely execution of development efforts by way of robust layout design
  • Review test data and perform analysis for calculation of robust test limits
  • Plan and execute product engineering activities required for new products
  • Collaborate with Design Engineers, Test Engineers, Applications Engineers, and Program Management to develop products that meet end customer requirements
  • Work with global SoC architecture team and design team to define/deliver best power/performance product
Qualifications for layout design
  • Must enjoy working in a dynamic, fast-paced environment while interacting with multiple sites in North America and Asia
  • MS degree of EE with 5+ years working experience in ASIC Company
  • Familiar with C/C++ programming and unix/linux and scripts (tcl, perl )
  • Work is performed with limited supervision
  • Possesses specialized knowledge of Computer architecture and computer arithmetic (a plus)
  • Possesses specialized knowledge of Computer graphic knowledge (a plus)
3

Layout Design Job Description

Job Description Example
Our company is looking to fill the role of layout design. Please review the list of responsibilities and qualifications. While this is our ideal list, we will consider candidates that do not necessarily have all of the qualifications, but have sufficient experience and talent.
Responsibilities for layout design
  • Cooperation with design, process, system product teams to deliver overall product pre-bounding box and power specification
  • Join in development of leading-edge display technologies
  • Use advanced verification methodologies for the verification of complex designs
  • Implement test plans, verification plans, testbenches and test cases and participate in test debug
  • We are currently looking for a SOC DV Technical staff (Senior Eng or Lead level) who will be part of a team working on next gen of a complex SOC design which include integration of GPU core, Multi-Media, IOs, The successful candidate will play a key role in SOC verification performing the following duties for functional, power, and performance aspects with simulation and hardware emulation environment
  • Support test automation infrastructure and develop test scripts
  • Debugging and troubleshooting system-level issues related to power/system management IP
  • Work in close collaboration with the front end designers and architects on the various SOC performance verification efforts
  • Interact with a wide variety of internal and external design verification development teams, DV methodology, and Silicon IP and tool vendors
  • Work with architects, and the design and DV team to develop functional and performance Test plan
Qualifications for layout design
  • Must enjoy working in a dynamic, fast-paced environment located in Markham but interacting with multiple sites in North America and worldwide
  • BS/MS in EE, CS, CSE plus 0-2 years hardware verification experience
  • Experience with Verilog, C/C++ required
  • Experience with SystemVerilog, OVM/UVM, SVA/PSL, or Perl a plus
  • Know DV flow
  • Know coverage
4

Layout Design Job Description

Job Description Example
Our growing company is looking for a layout design. We appreciate you taking the time to review the list of qualifications and to apply for the position. If you don’t fill all of the qualifications, you may still be considered depending on your level of experience.
Responsibilities for layout design
  • Responsible for multiple aspects in ASIC design flow and provide technically leadership to the engineering team
  • Apply verification and tools expertise to deliver I/O subsystems currently in development
  • Partner with other ICT and SoC architects to help define next-generation I/O subsystems
  • Provide architecture expertise across product lifecycle
  • Define, influence, and develop revamped end-to-end frontend flows and tools
  • Mentor and influencer within organization
  • Develop C++ Architecture model to support Architecture Exploration and predict power and performance for next generation Graphics
  • Collaborate with Graphics Architects and Design & Verification Team to coordinate, participate in, new feature modeling
  • Correlation and tune model with pre- and post- silicon design
  • Analysis of results for Trace workloads included games and synthetic tests
Qualifications for layout design
  • Sound understanding of design applications for both print and web operations is preferred
  • Experience in grocery ad and product design preferred
  • Excellent knowledge of Verilog, C, C++ and a scripting languages
  • Experience with low-level software/firmware is an asset
  • Experience with low level, physical phenomena oriented logic design is an asset (dealing with IO, clocking, voltage control)
  • 15 years of ASIC development experience with a complete understanding of the ASIC development flow, knowledge of ASIC semiconductor technology and manufacturing
5

Layout Design Job Description

Job Description Example
Our growing company is searching for experienced candidates for the position of layout design. Thank you in advance for taking a look at the list of responsibilities and qualifications. We look forward to reviewing your resume.
Responsibilities for layout design
  • Focus on algorithm verification or performance analysis to Graphics IP inside GPU
  • Create and execute SoC testplan including data-path and interrupt, virtualization, security, power management
  • Implement directed and random test cases/libraries in C++/SV, checkers and assertions
  • Architectural analysis and prototyping using C-model and arch model
  • Performance analysis for competitive performance
  • Work with various design leads to spec-out architecture
  • API formulation
  • Maintenance of existing FW encode solutions
  • Must be able to work with HW architects and HW designers and SW engineers to solve functional issues
  • Assist other FW engineers to develop FW support for new HW features
Qualifications for layout design
  • Knowledge of Computer Architecture, pipelined design, caches is required
  • Knowledge of 3-D graphics and microprocessor design is highly desirable
  • Strong communication skills, ability to multi-task across projects, and work with geographically separated teams
  • Master of Science Degree in Computer Science or Computer Engineering
  • Working knowledge of graphics pipeline
  • Minimum 5+ years design verification experiences, at least have 1+ years of DV experience at SOC level

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