RTL Design Engineer Resume Samples

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A McCullough

Aliza

McCullough

9690 Anastacio Lock

Houston

+1 (555) 881 6311

9690 Anastacio Lock

Houston

Phone

p +1 (555) 881 6311

Experience Experience

Boston, MA

RTL Design Engineer

Boston, MA

Heaney-Ryan

Boston, MA

RTL Design Engineer

Performance analysis and tuning of workloads on heterogeneous platform
Perform RTL coding
Communicate and work with team members across multiple disciplines
Work with Partners/Supplier to optimize and customize their products
Develop detailed design specifications
Developing UPI RTL code using Verilog for UP link/protocol layers
Designing and developing RTL code using VHDL or Verilog to accelerator kernels for linear algebra, graphical models, combinatorial logic, machine learning etc

Chicago, IL

Senior RTL Design Engineer

Chicago, IL

Bernhard Inc

Chicago, IL

Senior RTL Design Engineer

Assist in shaping the micro-architecture of the chip
Power management with multiple power domains
High-speed data path and control units
Pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation plus debug
Strong background in computer architecture including one or more of the following
Integer and floating point numeric units
Demonstrated track record of bringing logic designs into high volume production

present

Boston, MA

Principal RTL Design Engineer

Boston, MA

Roob-Kuhic

present

Boston, MA

Principal RTL Design Engineer

present

Work with micro architect to develop specifications for devices
Work with DV team to develop test cases and debug
Interface to IP cores provided by vendors
Work with the physical design teams in aiding the implementation of the functional blocks
Guide the physical design teams in aiding the implementation of the functional blocks
Usage of EDA tools, including simulators (NCVerilog, Modelsim), synthesis tools (DC), timing (primetime-SI)
Familiar with Altera FPGA placement and fitting techniques

Education Education

Bachelor’s Degree in Electrical Engineering

Indiana University

Bachelor’s Degree in Electrical Engineering

Skills Skills

Self driven individual and a good team player
Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision
Inherent sense of urgency and accountability
Ability to multi-task in a dynamic, fast-paced environment
Excellent verbal and written communication skills
Ability to interface internally and externally with all levels of the organization
MS in Engineering with 3+ years of experience, or BS in Engineering with 5+ years of experience in RTL design of submicron SOC products (eg: Microprocessor based SOC’s)

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15 RTL Design Engineer resume templates

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RTL Design Engineer Resume Examples & Samples

Defining architecture and microarchitecture of FPGA RTL stack for Intel UPI (Ultra Path Interconnect)
Developing UPI RTL code using Verilog for UP link/protocol layers
Validation and debug of RTL in simulations and FPGA prototype systems
Overseeing and guiding FPGA vendors for their UPI physical layer implementations
Performance analysis and tuning RTL on heterogeneous platform
Conversion of FPGA RTL to an ASIC design
Familiarity of computer architecture, operating system, and cache coherency
Familiarity of FPGA design tool flows
Ability to calculate and measure of system performance under various constraints
Strong technical and problem solving skills
Ability to work independently as well as in team environment

SOC RTL Design Engineer Resume Examples & Samples

Responsible for the logic implementation of complex design block(s) using RTL coding
Working with verification & validation engineers to define and review cluster level directed/random tests and environments
Provides support to SOC implementation teams on timing constraints/UPF definition
3-5 years of industry experience
A strong background in RTL level Digital IC Design using System Verilog, VHDL and/or Verilog
Experience with languages and standards such as VHDL, Verilog, System Verilog, Perl, Shell scripting, UPF
Expertise with Bus interface protocols like OCP, AHB, and AXI etc
Strong SOC design experience
Experience with industry standard design integration tools and methodologies
Experience in Lint checking/CDC methodologies
Experience in gate level simulations/debug and netlist ECO implementation
Good knowledge of Synthesis and Static Timing Analysis (STA) with Design Compiler and Primetime
Good knowledge of Conformal, Spyglass-LP, Spyglass-DFT etc., design quality check tools

RTL Design Engineer Resume Examples & Samples

Designing and developing RTL code using VHDL or Verilog to accelerator kernels for linear algebra, graphical models, combinatorial logic, machine learning etc
System debug & Validation of FPGA prototype systems
Performance analysis and tuning of workloads on heterogeneous platform
Bachelors or Master of Science degree in Electrical Engineering or Computer Science
2+ years of experience in hardware development using VHDL or Verilog or System Verilog
2+ years of experience with FPGA and/or ASIC design tools used for RTL development
5 or more years' experience with mapping various workloads to CPUs and accelerators, including implementing algorithms on FPGAs
Prior experience working with Heterogeneous (FPGA, GPGPU) hardware systems
Subject matter expertise in a particular class of algorithms, e.g. speech, cryptography, compression, image processing, etc
Ability to define and execute tasks with limited direction

DCG RTL Design Engineer Grad Intern Resume Examples & Samples

Must be pursuing PhD or Master's Electrical Engineering, Computer Engineering, Computer Science or other science/engineering related field
Verilog or other HDL
FPGA operation and capabilities
Algorithm design in heterogeneous computing environments or other nonstandard computer architectures
Application development
Source code development, control, review

Rtl Design Engineer Mts Level Resume Examples & Samples

Work with a team of hardware and software engineers to define the high-level architecture of sub blocks of Load Store unit
Ownership of RTL design for few complex blocks in Load store unit of the Core and contribute to Design Verification and Synthesis, floorplan efforts
Share in definition of micro architecture of next generation Core processor
8+ years of experience in high-performance design / micro-architecture
6+ years of experience in Verilog RTL development experience with industry tools in a CPU/SOC or ASIC environment
Background in other aspects of ASIC implementation, especially with Synthesis flow and Static Timing Analysis, is a plus
Likely candidate should have a MS EE/CS degree with 8+ years of experience

RTL Design Engineer Resume Examples & Samples

The ideal candidate will have 5+ years of experience in the following
Knowledgeable in modern design techniques
Knowledgeable in energy-efficient/low power logic design
Strong background in computer architecture including one or more of
High-speed CMOS processor and controller blocks
Cache controllers, bus-interface- subsystems, integer and floating point numeric units
Digital filters, graphics processors, crossbar fabrics and other high-speed data-path
Control units
Experienced in logic optimization, synthesis, timing analysis, floor-planning
Fluent with RTL Verilog/VHDL syntax and hardware modeling
Familiarity with logic simulation and debug environments as well as formal verification
Should exhibit excellent communications skills, and be self-motivated and well organized
GPU Design experience preferred

Senior RTL Design Engineer Resume Examples & Samples

Advanced knowledge of mixed signal concepts
Advanced knowledge of RTL design
Advanced knowledge of Verilog and SystemVerilog
Advanced knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
Good knowledge of synthesis, static timing, DFT, is a plus
Good knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus
Good knowledge of scripting languages. Perl and Python are plusses

Principal RTL Design Engineer Resume Examples & Samples

Lead the Architecture team
Shape the micro-architecture of the chip, and write specifications for the relevant block, micro-architecture of the block, design implementation using RTL coding techniques, Synthesis, place and route, and timing signoff
Lead the Verification team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation plus debug
Guide the physical design teams in aiding the implementation of the functional blocks
Self driven individual and a good team player
Inherent sense of urgency and accountability
Able to multi-task in a dynamic, fast-paced environment
Effective interpersonal, teamwork, and communication skills

Senior RTL Design Engineer Resume Examples & Samples

Advanced knowledge of Verilog and System-Verilog
Good knowledge of System-Verilog assertions, checkers, and other design verification techniques are a plus
Good knowledge of Algorithm developments
SERDES knowledge is a plus

Senior RTL Design Engineer Resume Examples & Samples

The ideal candidate will have 7+ years of hands-on experience
Strong background in computer architecture including one or more of the following
Tiered memory systems
Power management with multiple power domains
Encryption/security
Integer and floating point numeric units
Demonstrated track record of bringing logic designs into high volume production
Ability to work well in a team and be productive under aggressive schedules
Should exhibit excellent communication skills and be self-motivated and well organized

Senior RTL Design Engineer Resume Examples & Samples

BS in Electrical Engineering required, advanced Degree a plus
Top-notch problem solving skills, working within complex systems
Experience using FPGAs and understanding FPGA architectures
Experience with all stages in the ASIC design flow including verification methodologies and tools (UVM/OVM, Formal Checks, LINT tools, etc)
Experience using Revision Control tools - Subversion, RCS, CVS, or Perforce
Good communication skills – able to write design specifications, write test plans and conduct peer reviews and the ability to work well in a global, multi-site team

Senior SOC RTL Design Engineer Resume Examples & Samples

MS in Electrical Engineering or Computer Engineering
7+ years of experience architecting, writing and verifying complex RTL logic for SOC designs
Previous work experience designing clock and reset control logic for a complex SOC, preferably ARM-based
Previous work experience with physical design engineers to assist with the implementation flow, eg clock tree synthesis, floor planning and implementing ECO fixes
Previous work experience with verification engineers on simulation or emulation flows and familiarity with industry standard verification methodologies (UVM, assertions etc)
Previous work experience with AXI or other standard bus interface protocols
Previous experience scripting in Perl, TCL, or Python

Principal RTL Design Engineer Resume Examples & Samples

Implement logic designs in ASICs and FPGA for support of storage appliances
Work with micro architect to develop specifications for devices
Implement RTL to deliver needed functions
Interface to IP cores provided by vendors
Work with DV team to develop test cases and debug
Lab bring up using Signaltap
Digital Logic implementation of ECC, FIFOs, Asynch ckts (multiple clock domains)
Usage of off the shelf DDR4 controllers
Experience with clock speeds of up to 350MHz
Familiar or knowledge of NAND flash devices, and/or RAID implementations desirable
Strong design experience with PCIe IP
Usage of EDA tools, including simulators (NCVerilog, Modelsim), synthesis tools (DC), timing (primetime-SI)
Familiar with Altera FPGA placement and fitting techniques
Five years’ experience using Verilog, VHDL knowledge helpful
MSEE or Equivalent experience
Five to eight years’ experience with key role in products that have shipped
Significant experience with SR-IOV

Principle RTL Design Engineer Resume Examples & Samples

BSEE/MSEE with minimum 5 years industry experience. Must have worked on multiple IC's; taped-out and in production
Experience with USB Type C/ USB-PD, UVM a plus
Experience with other industry standard protocols USB3.0, SATA, PCI, DisplayPort, HDMI is desirable but not required
Experience with SOC designs with onchip ARM or 8051 microcontroller and hardware cryptography design experience is highly desirable
Candidate must be able to work under pressure and deliver on commitments with aggressive and challenging schedules
Must be handson and possess solid design and architecture experience for chip and system definition, low power design techniques, multiple power domain design, clock gating, multi VT deisgn, CPF and CDC tools

CPU Senior RTL Design Engineer Resume Examples & Samples

Minimum 7+ years of post-degree work experience in processor microarchitecture and RTL design
Prior experience in Core RTL and micro-architecture, out-of-order processor design
Prior experience in high-performance, low-latency execution, high area-efficient and power-efficient processor design
Excellent grasp of RTL design for multi-threaded, low-power microprocessors
Hands-on experience using Verilog or VHDL HDL for design
Experience designing for synthesis targeted to achieve specified power, frequency, and area targets

Digital RTL Design Engineer, Senior Resume Examples & Samples

5+ years experience with details of RTL development (VHDL and/or Verilog) including
Functional and structural RTL design, design partitioning
Simulation and regression, collaboration with design verification team

CPU RTL Design Engineer Resume Examples & Samples

Minimum 7 years of post-degree work experience in processor microarchitecture and RTL design
Subject matter expertise in integer and floating point arithmetic design, including wide single-instruction multiple data (SIMD) execution
Prior experience in low latency, area/power efficient multiplier, multiply-accumulate, divider, cryptographic design
Prior experience in Core RTL/uarch, out-of-order processor design (such as proficiency with Rename, Issue/Dispatch, Instruction Commit, Exception Logic)
An excellent grasp of RTL design for multi-threaded, low-power microprocessors
Hands on experience using Verilog or VHDL HDL for design
Interaction with validation team to contribute to validation strategy and help debug fails
Strong understanding of functionality, performance & physical implementation tradeoffs
Have the ability to travel occasionally for training and customer meetings

CPU RTL Design Engineer Resume Examples & Samples

Minimum 5 years of post-degree work experience in processor microarchitecture and RTL design
Prior experience in Core RTL and micro-architecture, processor designPrior experience in high-performance, low-latency execution, high area-efficient and power-efficient processor design
Subject matter expertise in various logic areas of CPU micro-architecture design
Strong scripting skills, e.g. with Perl, Python, etc
Ability to travel occasionally for training and customer meetings

PHY RTL Design Engineer Resume Examples & Samples

Strong fixed-point knowledge and extensive experience with bit-true verifications
Basic understanding of DSP communication algorithms and tradeoffs between performance and complexity
Knowledgeable in modern design techniques and energy-efficient/low power logic design
Background in computer architecture including one or more of the following
Bus fabric, especially APB/AHB/AXI
System debug architecture
High-speed data path and control units
Experience with FPGA and/or emulation platform desired
Ability to drive strong production test/QA methodologies desired

Micro Architect RTL Design Engineer Resume Examples & Samples

Education BS or MS in Electrical Engineering or Computer Engineering
Prior RTL design experience is required
An ideal candidate will have at least 2+ and maybe even more than 4+ years of work experience in microprocessor, SoC, memory controller and interconnect IP design

CPU Subsystem RTL Design Engineer Resume Examples & Samples

RTL design for ARM/PowerPC based CPU subsystems for Automotive group
CPU subsystem integration including architecting solutions with Marketing & Systems teams and IP designs to support CPU implementations
Micro-architecture definition for Automotive CPU subsystems and roadmap development for future products
Encouraging and influencing technological innovations in the team
Knowledge of Verilog/Logic design
Experience with ARM cores or Switch Fabrics is a must
Background on CPU Subsystems/SoC Front-end RTL design or IP design
Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,AXI, Memory(Flash, SRAM,DDR) and memory controllers will be preferred
Knowledge of Synthesis/LEC/Spyglass/RTL Power estimator
Experience in Low power designs with various Clock gating, Power Gating and DVFS techniques
Perl/C scripting
5-15 years' experience in CPU Subsystems or RTL design

Senior RTL Design Engineer Resume Examples & Samples

Assist in shaping the micro-architecture of the chip
Write specifications for the relevant block
Micro-architecture of the block
Design implementation using RTL coding techniques
Synthesis, place and route, and timing signoff
Pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation plus debug
Aid in the implementation of the functional blocks
Must possess good communication skills
Ability to multi-task in a dynamic, fast-paced environment
Ability to interface internally and externally with all levels of the organization

HW / RTL Design Engineer Resume Examples & Samples

Frontend digital design leading up to synthesis; system-level architecture and interface definition; microarchitecture and RTL development; developing HW blocks for wireless modem and debugging; some DFT and backend work
Functional verification and timing sign-off to physical design engineers
Expert-level coding experience in Verilog/VHDL/System Verilog
Experience in ASIC frontend design for cellular (HSPA/LTE) Modem Baseband or Wi-Fi PHY receiver and transmitter blocks in a leading chipset company; experience having designed HW blocks (e.g., MIMO detector, FEC encoder/decoder, FFT/IFFT, Baseband filter, Interleaver, Equalizer, Channel Estimator, etc.) and followed through multiple product development cycles from microarchitecture to silicon; in-depth understanding of SoC architectures, peripherals, buses/interconnects and power management
Expert in ASIC frontend design and synthesis tools (including Synopsys DC) and Lint/Formal Verification/CDC checking tools
Experience in developing test benches for functional verification, RTL debugging and timing sign-off; and in formal verification methodologies including UVM/OVM and System Verilog assertions
Experience in scripting and automation tools (perl/tcl/gmake/python)
Experience with VCS, Verdi, and Spyglass
Experience in DFT methodologies, formal verification tools and physical design is a plus
Understanding of bus architectures (AXI or similar), Baseband/RFIC interfaces, Network-on-Chip and various CPU/DSP architectures desirable
Experience in post-silicon debugging, working in lab environment with reference boards and FPGA prototypes desirable
Familiar with ECO flows and tools

RTL Design Engineer Resume Examples & Samples

BSEE/MSEE and at least 5+ years’ experience with the following
Verilog/System Verilog RTL coding, Logic/Digital Design of digital communications and signal processing functions
Simulation and initial synthesis of RTL targeting FPGA and/or ASIC
Knowledge of wireless communications systems and standards, such as LTE and UMTS
Experience in modem design and verification
Experience with revision control systems such as Clearcase or GIT
Experience with tools such as VCS, NCSIM, Verdi, and Spyglass
Experience with Lint, CDC, Synthesis, equivalence checking
Experience with Multiple Clock Domains and Asynchronous Interfaces

RTL Design Engineer Resume Examples & Samples

Communicate and work with team members across multiple disciplines
Develop detailed design specifications
Perform RTL coding
Work with Partners/Supplier to optimize and customize their products
Run industry standard code quality tools and fix issues found by them
Participate in test plan and coverage reviews
5 years of practical experience
Experience working with 3rd party development projects
Experience with design development using Verilog
Experience with design verification, synthesis, timing/power analysis and DFT
10 years or more of practical experience
Experience with wide variety of low power design techniques
Large breadth of knowledge from architecture through physical design
Knowledge of FPGA and emulation platforms
Proficient with writing automation scripts
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SOC RTL Design Engineer Resume Examples & Samples

Scripting ability in Perl, TCL, Python or other similar languages
Writing RTL
RTL simulation and familiarity with industry standard verification methodologies such as UVM and assertions

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