Asic Design Engineer Resume Samples
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Asic Design Engineer Resume Samples
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DW
D Walter
Dominique
Walter
51665 Quinten Cove
Boston
MA
+1 (555) 683 3857
51665 Quinten Cove
Boston
MA
Phone
p
+1 (555) 683 3857
Experience
Experience
Dallas, TX
Asic Design Engineer
Dallas, TX
Ankunding and Sons
Dallas, TX
Asic Design Engineer
- Work closely with algorithm engineer to develop/debug new IP/product
- Knowledge in networking and networking chips
- Simulation, Design constraints, Coding Style checking, Cross clock domain checking, Synthesis and timing closure,
- Supervises and works closely with layout engineers
- Assist in verification of new System on Chip architectures, functions and components
- Developing designs using Verilog/VHDL
- Create and implement complete design verification environments
Houston, TX
MTS Asic Design Engineer
Houston, TX
Trantow, Reichel and Marks
Houston, TX
MTS Asic Design Engineer
- Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager
- Can solves complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation
- Analyze gating efficiency report to improve RTL quality
- Define verification plan, develop testbench, write/debug tests, analyze coverage report to achieve verification closure
- Co-work with design team for architecture discussion and RTL debug
- Participate graphics IP block-level verification work
- Know the whole flow of verification
present
Phoenix, AZ
Senior Asic Design Engineer
Phoenix, AZ
Pouros LLC
present
Phoenix, AZ
Senior Asic Design Engineer
present
- Work with system architect to define spec/micro-architecture and RTL development
- Knowledge of high performance coherent memory system or interconnect architectures
- Develop stressful testplan
- Create testcase to ensure maximum coverage
- Work with physical implementation team to address Synthesis, Place & Route, Timing and DFT issues
- Develop verification IP which can be reused at different levels of verfication: block level, sub-system level, SoC level, etc
- Work with RTL designer to get a full deep insight on the design under test
Education
Education
Bachelor’s Degree in Electrical Engineering
Bachelor’s Degree in Electrical Engineering
Ohio University
Bachelor’s Degree in Electrical Engineering
Skills
Skills
- Strong knowledge of Verilog and C
- Deep knowledge in Verilog
- Good oral/written English skills
- Good communicator
- Able to work in multi-disciplinary team environment and provide feedback
- Strong execution orientation
- Script knowledge (TCL, perl, etc.)
- Excellent communication skills in English (written and verbal)
- Knowledge in networking and networking chips
- Strong communication, presentation and documentation skills
15 Asic Design Engineer resume templates
Read our complete resume writing guides
1
Senior Asic Design Engineer Resume Examples & Samples
- Hands-on experience in block level and full-chip industry standard ASIC EDA tools like Synthesis, P&R and Timing including timing constraints generation and management
- Expertise in analyzing and converging timing, noise and electrical rules, and understanding the performance and power sensitivity to design and integration choices
- Hands-on experience with circuit design and optimization across a diversity of circuit types for performance, power and area on deeply-scaled CMOS technology nodes
- Knowledge of standard circuit simulators like SPECTRE and/or HSPICE, and the ability to model and simulate circuits and automate for analysis and results reporting
- Good ability to develop, maintain, support, document, and enforce standard cell/ASIC and custom/IP product design and integration methodologies
- Motivated, flexible and open to a variety of tasks, and excellent and demonstrated team player with the ability to work with cross-functional teams
- Proficiency in scripting language, such as, Perl and/or Tcl to automate large tasks and analyze large amounts of data
2
Senior Asic Design Engineer Resume Examples & Samples
- Work with RTL designer to get a full deep insight on the design under test
- Develop stressful testplan
- Build testbench
- Create testcase to ensure maximum coverage
- Develop verification IP which can be reused at different levels of verfication: block level, sub-system level, SoC level, etc
3
MTS Asic Design Engineer Resume Examples & Samples
- Participate graphics IP block-level verification work
- Define verification plan, develop testbench, write/debug tests, analyze coverage report to achieve verification closure
- Co-work with design team for architecture discussion and RTL debug
- Support IP level verification team
- Major in EE & CS
- Know the whole flow of verification
- Should be familiar with shell/perl/tcl programming in linux OS
- Will be a plus if having Verilog coding, debugging and modeling experience
- Will be a big plus if having OVM/UVM experience
4
DFT Timing Lead-asic Design Engineer Resume Examples & Samples
- Coordinate and communicate with physical design and front-end design team to refine STA constraints and close DFT timing at SoC level and block level
- Create and maintain DFT timing constraints (e.g. clock definition, timing exceptions…etc)
- Compare SCAN cell reports with timing reports to identify hold/setup issues
- Review and debug macro/memory timing models
5
Camera Asic Design Engineer Resume Examples & Samples
- ASIC design for next generation of Camera processors
- Micro architecture definition and specification documentation
- RTL design, verification, emulation, synthesis, timing, and silicon bring-up
6
Senior.asic Design Engineer Resume Examples & Samples
- High expertise in mixed signal ASIC design, and verification
- Extensive Tools usage for ASIC Chip design : Cadence/Mentor Graphics/Synopsis
- VHDL or Verilog Programming skills. RTL programming
- RTL coding and simulation Test bench development for the verification of RTL blocks
- Experience in Formal Verification
- Worked previously with Fab houses and chip manufacturers, would be advantageous
- BS / MS / PhD in Electrical/ Electronics / Computer Science
- V. Good knowledge of analog electronics is a nice to have
- Good debugging and problem solving skills
- Good communication skills and ability & desire to work as a team player are a must
7
Digital Asic Design Engineer Resume Examples & Samples
- Micro-architecture development in close cooperation with architects and peers
- Design of complex ASIC architectures using Verilog
- Use of internally and externally developed IP in Verilog or VHDL
- Verification of design at a module level and design of test benches
- Use of a variety of EDA tools for design and verification as well as RTL synthesis
- MSEE or equivalent required
- 3-5 years of professional experience of ASIC design required
- Experience with Verilog or VHDL and related simulators required
- Experience with ASIC verification is required
- Experience from other languages such as C/C++, Tcl, Perl is a benefit
- Experience from ASIC backend aspects is a benefit
- Located in the Copenhagen area or willing to relocate. In possession of an EU work permit
8
Fpga / Asic Design Engineer Resume Examples & Samples
- Participate in the micro architecture and design partition within the ASIC/FPGA
- Bring-up and validate ASICs and FPGAs in the lab
- 3+ years of experience working with complex FPGAs and/or ASICs
- 3+ years of experience in Verilog / System Verilog and/or VHDL
- Ability to solve complex problems including clock domain crossings and power optimization
- Experience with latest simulation and verification methodologies
- Exposure to timing closure techniques
- Experience with high reliability design and implementations
- Excellent scripting skills (csh/bash, Perl, Python etc.)
- Experience with EDA tools such as HDL simulators (VCS, Questa, IES), HDL Lint tools (Spyglass), FPGA tools (Xilinx Vivado, Altera Quartus II)
9
Principal Asic Design Engineer Resume Examples & Samples
- Communications/DSP and packet processing algorithms, and efficient implementations
- Digital IC design, design for low power and high speed, design for test (DFT)
- System modeling, RTL coding, Lint/CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence/Synopsys design environments
- Verilog/System Verilog, C, and scripting languages
- Embedded systems FPGA emulation, lab debug and silicon performance validation
- Self-motivated, excellent communication skills and ability to excel and to provide leadership in a team environment
- MS + 12 years’ experience, or Ph.D. + 10 years' experience
10
Senior Asic Design Engineer Resume Examples & Samples
- The ideal candidate will have at least 10+ years of ASIC design experience from spec to high volume production (15+ is preferred)
- Design experience in high performance Cache controllers (Load store unit for CPU, CPU cache controller, SOC cache controller, or GFX cache controller)
- Design expertise in Cache controller architecture/Micro-architecture definition, RTL design for high performance, low area, and low power
- Strong knowledge of memory system PPA (performance/power/area) analysis
- Strong cache design background including good understanding of different memory organizations and trade offs
- Knowledge of high performance memory subsystem and dram controller is a plus
- Knowledge of low power design techniques is a plus
11
Analog Asic Design Engineer, CSM Resume Examples & Samples
- 3+ years of experience in managing digital design teams
- Hands on experience with FPGA emulation, silicon bring-up, characterization and debug
- Must be able to work with cross-functional teams within Apple and external vendors across geographical boundaries to resolve architectural and implementation challenges with an eye towards schedule
12
Senior Asic Design Engineer Resume Examples & Samples
- The ideal candidate will have 5+ years of ASIC design experience
- 5+ years of development of memory system
- 5+ years of RTL/micro-architecture definition
- 5+ years of experience in PPA (performance/power/area) analysis
- Knowledge of high performance coherent memory system or interconnect architectures
- Knowledge of high performance memory subsystem and dram controller
13
Asic Design Engineer Resume Examples & Samples
- The candidate will have a Bachelors degree in EE with 7+ years of work experience or Masters degree in EE with 5+ years work experience
- 5+ years of RTL Logic Design experience of multi-million gate ASICs
- Experience in writing specifications and converting them to design
- Experience designing high performance, low power ASICs/SOCs from scratch
- Exposure to timing closure on high speed, low power designs
14
Senior Asic Design Engineer Resume Examples & Samples
- The ideal candidate will have 15+ years of ASIC design experience
- A demonstrated history of technical leadership
- 5+ years of architecture research and/or development of memory or highly interconnected system architectures
- 5+ years of research and development experience in PPA (performance/power/area) analysis
- Very good understanding of traffic scenarios in an SOC environment and differentiation of service for them
- Systems experience in characterizing performance, doing comparison studies, and documenting and publishing results
15
Asic Design Engineer Resume Examples & Samples
- The ideal candidate will have a Bachelors degree in EE or CECS with 5+ years of work experience or Masters degree in EE or CECS with 3+ years work experience
- Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies
- Experience writing specifications and converting them to design
- Experience with multiple clock domains and asynchronous interfaces
- Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs is highly desirable
- Ability to communicate effectively across all internal groups
- Familiarity with software and operating concepts a plus
- Familiarity with scripting languages like Perl or Tcl a plus
16
Senior Asic Design Engineer Resume Examples & Samples
- This position requires thorough knowledge of the ASIC design flow, front end RTL coding and Design verification, synthesis, scripting and netlist generation
- The ideal candidate will have the following background
- At least 10+ years experience in ASIC design flow
- Expertise in at least one of the following disciplines
- CPU load store units or BIU unit design
- L1, L2, or larger on chip or off chip cache design
- Coherent memory system design
- SOC system bus design
- Memory controller design
- Networking packet based bus protocols
- Proven track record of complex high performance designs in high volume production for low power applications
- Design for high performance, low area, and low power
- Familiarity with CDC, DFT, UPF, other Asic flow checks, and backend timing closure at hihg frequencies is a plus
- Strong communication skills are a pre-requisite as the candidate will interface with a lot of different people within and outside the company
- Self starter and highly motivated
17
Senior Digital Asic Design Engineer Resume Examples & Samples
- Logic synthesis using Synopsys Design Compiler
- Estimating and scheduling your work so that progress can be managed by our in-house program management group
- Writing scripts using languages such as Tcl and PERL to achieve higher performance and improve productivity through automation
- Bachelor of Science degree in electrical engineering, computer science or computer engineering
- 7+ years of work experience
- 3+ years of experience in scripting languages (perl, tcl, make or shell)
- Programming proficiency using Verilog/System Verilog
- Familiar with ASIC design methodology/flows/checks for digital designs
- Problem solving skills with appropriate attention to detail
- Experience with synthesis tool and flow to generate high quality netlists for various blocks
- Good coordination and problem solving skills and ability to meet tough goals under high pressure
- Self-directed and motivated to be successful in a fast paced environment
- Strong interpersonal, written and verbal communication skills
- Knowledge of wireless communications systems and standards, including 4G LTE (FDD/TDD). Experience in modem design and verification
- Experience/knowledge in the architecture/RTL design of signal processing wireless protocols including 802.11a/b/g/n/ac or hands-on experience in any of one of LTE/WiMAX/4G/Gigabit DSP preferable
- Knowledge of wireless communications systems and standards, including LTE (FDD/TDD) and UMTS. Experience in modem design and verification
- Experience with revision control systems such as Subversion or GIT
- Experience with scripting languages such as TCL, Python, or Perl
- Experience in the design and implementation of high speed forward error correction (FEC) codecs, such as Turbo Codes, LDPC, convolutional, and Reed-Solomon codecs
- Experience with DPI-C, System Verilog, UVM
- Experience with C/C++, Python, Matlab and/or other simulation and modeling tools/languages
- Experience in PCIe, Ethernet and DDR interfaces and understand their I/O protocols
- Experience in AMBA bus architecture and its protocols
18
Asic Design Engineer Resume Examples & Samples
- Member of the design team that is responsible for developing complex, state of the art high-speed Ethernet controller chips
- The candidate will own tasks such as micro-architecture, design, integration and other tasks as part of the chip development and testing processes
- 5+ years of experience in VLSI design
- Deep knowledge in Verilog
- Experience in micro-architecture and design of complex blocks
- Familiar with the verification process of a block (test plan, coverage, etc.)
- Excellent communication skills in English (written and verbal)
- Knowledge in networking and networking chips
- Experience with multi-clock domain designs
- Script knowledge (TCL, perl, etc.)
- Understanding the timing closure process (synthesis/STA)
- Understanding DFT
- Understanding the entire chip development flow
- Strong execution orientation
- Thorough and accurate
- Open minded
19
Asic Design Engineer Resume Examples & Samples
- BS in Electrical Engineering, Computer Engineering, or comparable engineering discipline
- 9+ years of relevant experience (7+ years with an MS, 4+ years with a PhD)
- Experience with full product life cycle (requirements, design, implementation and test) of ASIC Design
- Working knowledge of low power microarchitecture techniques
- Strong RTL implementation, Synthesis and Static Timing Analysis skills
- Be able to work in teams and communicate clearly across various levels of management and engineers
- MS in Electrical Engineering, Computer Engineering, or comparable engineering discipline
- Experience with Mentor Graphic’s Questa, Synopsys, Cadence or similar tools
- Experience with advanced node ASIC technologies and experience with Global Foundries
- Experience with scripting languages such as TCL, Python or Perl
- Part of a team with a successful tape out of multi-million gate ASIC
- Familiarity with ASIC technology and designing for security
- Active DOD Top Secret Clearance
20
Analog Asic Design Engineer, CSM Resume Examples & Samples
- 2+ years of technical management experience
- Direct experience and in depth understanding of analog circuit design specifically op-amps, LDO, PMU, PLL, high-speed CDR and SERDES
- Hands-on design experience with Cadence schematic capture and simulation tools
- Experience with all phases of product development cycle from definition to transfer to production
- Hands-on experience with analog circuit design, chip integration, verification and validation
- Direct involvement with ATE test plan development, review of results and limit setting
- Familiarity with Digital design and PCB signal integrity is a plus
- Some travel is involved
21
Principal Asic Design Engineer Resume Examples & Samples
- Develop network processing ASIC/FPGA architecture and micro architecture specification
- Design high performance and high quality ASIC/FPGA design from specification to RTL implementation
- Perform ASIC/FPGA verification, synthesis, timing analysis IP integration
- Implement network packet processing system using Altera/Xilinx FPGA
- Participating system/board level bring up, debugging and support
- 8 years or more networking or processor experience
- Strong tracking record of ASIC/FPGA design from concept to mass production
- Hands-on experience on Verilog HDL coding and verification
- Experience of high performance ASIC/FPGA design from specification to system bringing up
- Experience with Altera/Xilinx FPGA architecture, tools and IP portfolio
- Ethernet and TCP/IP networking concept and protocols knowledge
- Knowledge of System Verilog and UVM verification methodology
- Highly motivated, positive, detail oriented and responsible
- Good team player and good communication skills
22
Senior Asic Design Engineer Resume Examples & Samples
- Subchip development in large mixed signal ASICs
- Work with system architect to define spec/micro-architecture and RTL development
- Synthesis and optimisation for design size/timing/power trade-off
- Layout support for quality final product and TTM
- B.Sc. in Elec/Computer Engineering is a must, higher degrees preferred
- 2-5 years of experience in ASIC design
- Solid design (micro-architecture/implementation) and debugging skills
- Working knowledge of DSP/FEC and communication theories
23
Asic Design Engineer Resume Examples & Samples
- Proven track record of contributing to the development of ASIC based products by assisting with the overall conception, design and optimization of digital and analog ASIC circuits
- Experience writing complex RTL code for ASIC based products using industry standard Hardware Description Languages
- Proficiency performing analog and digital simulations using standard industry simulators
- Knowledge and experience performing static timing analysis/debug and implementing design improvements
- Experience performing sub-block, block and chip level logic synthesis using industry standard tools
- The ability to direct the Physical Integration team with floor-planning and physical partitioning of the design
- Prior experience in disk controller or storage design is a plus
24
Asic Design Engineer Resume Examples & Samples
- Block and system level micro-architecture design, including architecture trade-offs for pre-silicon FPGA emulation
- Verilog/SystemVerilog RTL implementation
- Digital simulation and debug utilizing a UVM test-bench and simulation environment
- Implementation in custom Xilinx FPGA platforms for pre-silicon emulation
- Supporting FPGA emulation and debug, including compliance and interop testing
- Synthesis, formal verification, and static-timing analysis efforts leading to ASIC stream-out
25
Digital Asic Design Engineer Resume Examples & Samples
- Two years or more experience of digital RTL design experience
- Knowledge of digital logic design best practices
- Detailed understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation, and equivalence checking
- Understanding of Design Verification and the ability to write self-checking test suites and debug/triage failures
- Experience writing assembly and high level code is a highly desirable
- Knowledge of a scripting language such as Perl, Tcl, C shell
- Experience in hands-on lab evaluation including the use of digital multi-meters, oscilloscopes and logic analyzers
- Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation is desirable
- Experience with verification environments and languages, preferably System Verilog, and assertion based verification is desirable but not required
- Familiarity with UVM is desirable but not required
26
Asic Design Engineer Resume Examples & Samples
- Develop and unit-test ASIC blocks and components of subsystems (in some cases involving FPGAs) from
- 0-5 years of relevant work experience
- Experience in basic projects in logic, ASIC, VLSI, and FPGA
- Comfortable in Verilog and SystemVerilog for development of simple and complex logic
- Aware of ASIC design flow. Experience with some frontend design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis. Exposure to backend tools a
- Exposure in to some major IP and protocols, such as SERDES, PCIe and
- Familiar with the theory behind DFT, BIST, other DFx
- Good scripting skills (e.g. Python, Perl,
- Familiarity with verification methodologies and emulation or prototyping experience
- Problem-solving and debug skills. Can decide the path to isolate a problem and can infer what a result
- Energetic. Self-driven. Good communication, organization, analytical, presentation and people
- Does not wish to be confined to a small focused role. Driven to understand the big picture. Can easily switch gears and take on new and diverse
- Willing to learn and develop as an engineer
27
Senior Asic Design Engineer Resume Examples & Samples
- As a Senior Design Engineer you’ll help design, implement and verify complex products that use FPGAs and/or ASICs
- Work with physical implementation team to address Synthesis, Place & Route, Timing and DFT issues
- Work with backend teams to address layout and timing issues for ASICs
- 8+ years of experience working with complex FPGAs and/or ASICs
- 8+ years of experience in Verilog / System Verilog and/or VHDL
- Master’s degree in engineering or math
- Familiarity with VHDL is a plus
- Experience in implementing digital signal processing is preferred
- Experience with C and C++ programming is desired
- Understanding of Datapath Pipelines, State Machines, Arithmetic Operations
28
Junior Asic Design Engineer Resume Examples & Samples
- Master degree or above in Microelectronics or Electronics Engineering major
- Good knowledge of analog building blocks (e.g. voltage, current reference, amplifiers, and regulators)
- Experience with analog DEA tools (e.g. Cadence, spectre, spice)
- Knowledge on semiconductor physics and manufacturing technologies
- Self motivated, excellent communication skills and team spirit
- English written and verbal; German as a plus
- Willingness to work and interact in international teams
29
Senior Asic Design Engineer Resume Examples & Samples
- Bachelor degree in microelectronic circuits or systems(Master more preferred)
- > 3ys experience in analog circuits design
- Good understanding of ASIC analog and mixed signal flow(Cadence based)
- Experience in ADC/DAC converter, switch-cap circuits design
- Hands-on experience in silicon evaluation and debugging
- Very good communication skills, team work and flexibility
- Foreign languages: English, German (as a plus)
30
Digital Asic Design Engineer Resume Examples & Samples
- Architect, design and verify digital and mixed signal ASICs that meets customer schedule and quality requirements
- Specifically, lead the verification and validation of ASICs utilizing industry standard verification methodologies such as UVM or OVM
- Extend and expand the verification effort through the use of external verification partnerships
- Specify and lead the verification architecture, planning, and methodology of all digital and mixed signal ASICs that meets customer schedule and quality requirements
- Manage and lead the verification planning and execution internally and with external partners
- Understand measurement products and systems and translate end customer requirements into the creation of the appropriate verification methodologies and the appropriate level of verification rigor
- Improve and automate established ASIC tools and verification methodologies to increase productivity, quality, and effectiveness
- Integrate and interface with high performance analog measurement circuits and employ mixed signal verification methodologies and tools to verify electrical and functional performance
- Secondarily, participate in the entire spectrum of full ASIC design activities including definition, architectures, digital logic design, IP validation, and synthesis
- BS/MS in Electrical Engineering
- Ten or more years in the direct design and verification of digital and mixed signal ASICs and DSP designs
- Expert knowledge in the different industry standard verification methodologies such as UVM or OWM
- Experience in managing and leading external partners in ASIC verification
- Strong proficiency in software models and how these models are used in the control and programming of an ASIC
- Strong EE fundamentals with experience ASIC Design, digital logic, digital architectures/systems, signal processing, and verification of large and mixed signal ASIC designs
- Proven technical leadership skills to gain credibility and respect to drive change and influence teams and partners towards higher levels of execution, return, and productivity
- Ability to multi-task and lead multiple projects, engineers, and partnerships
- Deep understanding of ASIC design flow, methodologies, and process
- Practical experience in working with external design partnerships and leading technical teams
- Some experience in the validation and verification of ASICs through methodologies such as SW co-simulation, HW emulation, and FPGA prototyping
- Experience in Verilog/System-verilog design
- Knowledge of semiconductor devices and structures
- Understanding of analog design basics
- Understanding of digital ASIC design methods and tools
- Strong multi-tasking and teamwork skills
- Ability to understand systems and digital architectures
- Strong understanding of engineering mathematics
31
Senior Fpga / Asic Design Engineer Resume Examples & Samples
- Bachelor's Degree in Electrical Engineering
- 6 years experience in digital design ASIC/FPGA experience
- Extensive experience in ASIC/FPGA design and verification flows
- Understanding of modern verification practices including System Verilog, UVM and assertion based test
- Experience and knowledge of communications standards (such as Ethernet, OTN, Interlaken)
- Experience with Xilinx tools and flow
32
Principal Asic Design Engineer Resume Examples & Samples
- RTL design of digital circuits using hardware description languages such as Verilog and System Verilog
- Documenting High level description of designs and requirements for signal processing subsystems
- Writing functional test cases to verify and debug digital designs
- A self-starter with the ability to manage your own time effectively, and the ability to work well in a diverse team environment
- 12+ years of work experience
- 3+ years of experience in developing automated, self-checking Test benches
- 5+ years of experience in STA, timing constraints and closure on high speed, low power designs
- Masters of Science in electrical engineering, computer science or computer engineering
- Experience with revision control systems such as subversion, ClearCase or GIT
- Digital design and verification, digital communications, and signal processing
- Experience with Synopsys synthesis and timing analysis tools
- Experience in Wi-Fi and/or other wireless networking. Experience in 802.3 and network processing
33
Asic Design Engineer Resume Examples & Samples
- RTL Coding, including block design, top level design, Lower power design, CPF/UPF design
- Bug analysis and fixing, Formal check
- Area, Power, FIT estimation/measure, DFT related, ATE support
34
Principal Asic Design Engineer Resume Examples & Samples
- 10+ years of experience in ASIC Design
- Participation in at least 1 full ASIC cycle as a designer from Arch to Bringup
- Good knowledge and experience in RTL/Synthesis based ASIC design methodology and tools
- Proven experience in the architecture of complex ASICs/FPGAs
- Experience in DSP/FEC based technology is preferred
- Networking and packet based protocol experience is preferred
- Experience in SONET, OTN or Ethernet based technology is preferred
- Must have ability and desire to work as a team
- Candidates must have a Bachelor's Degree or higher in Electronics and Communication/VLSI/Microelectronics with very good academics. Master’s degree preferred
35
Asic Design Engineer Resume Examples & Samples
- Knowledge of mixed signal design experiences
- Knowledge of analog design activities from concept to production, including specification definition, architecture design, schematic design, simulation, layout, manufacturing and silicon debugging/characterization
- Knowledge of required tools for analog IP development (eg. Spectre, HSPICE, Virtuoso, Calibre)
- Knowledge of high speed interfaces (eg. DDR, PCIe), on chip power management circuits (eg. LDO)
- Knowledge with advance storage IC design (eg. SSD, HDD, read channel)
- Knowledge of System Verilog, and capable of developing behavior model of analog circuitries for RTL simulation
- Knowledge of C or C++
36
Asic Design Engineer Resume Examples & Samples
- Develop software infrastructure and modeling for validation of SSD controller components
- Architect and implement test-bench for block level and full chip verification
- Generate tests, simulation and debug the Verilog design
- Create and implement complete design verification environments
- Provide hardware design and FPGA (Field Programmable Gate Array) simulation for hardware bring-up
- Experience in storage market and knowledge of flash media
- Experience in SSD controller architecture
- Experience in constrained random simulation and coverage driven verification
- Experience with Universal Verification Methodology (UVM) testbench
- Experience with Verilog and System Verilog Assertions (SVA)
- Experience in developing test using C/C++/ARM instruction and verifying ARM based SoC simulation
- Experience in writing firmware like test programs to run on embedded processors for SSD controller engines
- Experience in developing automated flow using Perl or Shell scripts
- Experience with gate level simulation involving SDF
- Experience with FPGA and silicon bring-up
- Experience with debugging simulations using simvision or Verdi
- Experience with AMBA protocols and NAND Interfaces
- Must be willing to work evenings or weekends, if necessary
37
Asic Design Engineer Resume Examples & Samples
- Reviewing architecture specifications
- Developing and implementing micro-architectures/design specifications
- Developing designs using Verilog/VHDL
- Implementing assertions and running synthesis and static timing
- Potential to support integration of fabric and blocks
- Reviewing verification test plans
- Supporting post-silicon validation
- Experience using hardware description languages (Verilog, VHDL)
- Experience with industry-standard EDA tools; specifically synthesis and/or static timing analysis
- Experience with state of the art verification techniques; assertion-driven coverage metrics, weighted pseudo-random testing
- Experience with ARM SOC based VLSI chips
38
Lead Asic Design Engineer Resume Examples & Samples
- Owner of ASIC design methodology. Responsible for design flow improvements
- Work with multi-site design team from IC project inception through initial production ramp
- Responsible for development schedules and maintain the schedule throughout the design phase
- Perform RTL-level design, including micro-architectural definition, of digital logic used in secure ASIC cores
- Develop product documentation for both internal and external audiences
- 10+ years of experience in hardware design, 2+ years of technical lead
- Must have good communication skills and takes responsibility for independent planning and executing of all aspects of secure hardware design
- Self-motivated, independent worker with strong leadership skills
- Experienced with front-end ASIC design flows, including design, simulation, synthesis, and timing analysis. Experience with back-end flows, especially place-and-route, is beneficial
- Proven track record of on-time delivery of silicon-proven designs
- Demonstrated proficiency in Verilog and digital design
- Expertise in some or all of the following areas is beneficial
39
Asic Design Engineer Resume Examples & Samples
- Design high performance and low power analog and mixed signal blocks
- Leads the definition, design, layout and characterization of various analog circuits: voltage regulator, PLL, bandgap reference, AGC, ADC, etc
- Leads IP definition, evaluation, and integration
- Supports chip integration for floor planning and tape-out
- Supervises and works closely with layout engineers
- Leads silicon validation of critical analog and mixed designs
- 5+ years of working experience in mixed signal design
- Hands on experience with chip bring-up
- Experience with Cadence design environment, HSPICE, MATLAB, Verilog-A
- Ability to work with people across multiple functional areas
- Familiar with Linux environment and scripting languages such as Bash and Perl
- Excellent analytical, problem-solving and organizational skills
- Proficient in written and verbal English
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Ethernet Asic Design Engineer Resume Examples & Samples
- Bachelor's or Master’s degree in Electrical Engineering
- 6 (+) months experience in digital logic design with RTL Verilog or VHDL
- 6 (+) months experience in ASIC development flow
- Experience with parameterizable automation of logic generation and verification
- Experience with implementing and verifying digital logic
- Experience with hardware debugging and validation using equipment such as function generators, oscilloscopes, and testers
- Excellent verbal and written communication, collaboration skills, and cross-functional leadership
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Digital Asic Design Engineer Resume Examples & Samples
- Utilize high-level architectural documentation along with algorithm description and implement DSP functions for functions such as decimation, interpolation, general filtering, up-down conversion, digital beamforming, channelization, and be able to develop mathematical models in SystemVerilog to verify design implementation and develop and run scripts and Makefiles
- Experience in Digital ASIC design and verification
- Experience with ASIC development including architectural definition, detailed design implementation using SystemVerilog, and functional verification using SystemVerilog
- Experience with design architecture and detailed specification generation
- Knowledge and competency of UVM
- Thrive in working within a fast-paced environment and work well in a team of ASIC engineers and Subsystem engineers
- Demonstrated history of 1st pass success with ASIC designs
