Physical Design Engineer Job Description
Physical design engineer
provides expertise and contribution to all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Physical Design Engineer Duties & Responsibilities
To write an effective physical design engineer job description, begin by listing detailed duties, responsibilities and expectations. We have included physical design engineer job description templates that you can modify and use.
Sample responsibilities for this position include:
Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors
Drive frontend and backend implementation from RTL to gds2, including synthesis, FV, floorplanning, netlisting, timing constraints, timing and power convergence, and ECO implementation
Would be responsible for hands-on physical implementation and timing closure of core platforms and SoC's
Working with Systems and Application team to drive timing closure friendly SoC architecture and IO interfaces/IO pin
Streamlining the timing signoff criterions, timing analysis methodologies and flows (critical path spice simulation ) and develop/enhance auto ECO generation scripts for timing closure
Responsible for floor planning , physical synthesis and physical design closure of large complex designs at 1GHz+ clock cycles
Synthesis engineer for a low-power SoC
Drive physical design and timing convergence of high-frequency low-power CPU, GPU, and/or ASIC at block level, cluster level, and/or full chip level
Clock distribution and CTS for 1 GHz+ designs
Extraction
Physical Design Engineer Qualifications
Qualifications for a job description may include education, certification, and experience.
Licensing or Certifications for Physical Design Engineer
List any licenses or certifications required by the position: RCDD, VLSI/CMOS
Education for Physical Design Engineer
Typically a job would require a certain level of education.
Employers hiring for the physical design engineer job most commonly would prefer for their future employee to have a relevant degree such as Master's and Bachelor's Degree in Electrical Engineering, Computer Engineering, Design, Computer Science, Engineering, Electronics, Science, Technical, Electronics Engineering, Communication
Skills for Physical Design Engineer
Desired skills for physical design engineer include:
Circuit design
FinFET technology
Package design
Extraction and STA methodology and tools
CAD automation methods
Timing closure
Synthesis
Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes
DFT
Full design cycle from RTL to GDSII
Desired experience for physical design engineer includes:
Motivation for layout automation, methodology development, SOC layout views and data conversion is desired
Versatility with scripts to automate design flow
7+ years of experience in large VLSI physical design implementation on 40nm, 28nm or 20nm or 16ff or 14nm technology
Successful track record of delivering designs to production is a must
Experience leading small teams (3-5) is a plus
Should be a power user of P&R and timing analysis CAD tools from Synopsys (ICC/DC/PT/STAR-RC/ICV), Cadence (First Encounter/Innovus/Voltus), Mentor ( Olympus )
Physical Design Engineer Examples
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Physical Design Engineer Job Description
Job Description Example
Our innovative and growing company is searching for experienced candidates for the position of physical design engineer. Thank you in advance for taking a look at the list of responsibilities and qualifications. We look forward to reviewing your resume.
Responsibilities for physical design engineer
- Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation
- Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level)
- Active participation in post silicon validation, correlation and test activities using in-house test and validation lab
- Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change
- Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow
- Perform custom RF Physical Design, including block-level and top level layouts, floorplanning, package routing
- Supports complex projects or leads smaller independent design activities
- Support CAD and drawing updates on both sustaining/new project with minimal supervision
- Completes multiple design cycles of moderate complexity with little supervision
- Contributes to PD architecture/Plug-In Unit at the unit level
Qualifications for physical design engineer
- Proficiency using Perl, Tcl, Make scripting is preferred
- 3+ years of experience in above areas
- 4+ years of experience in large VLSI physical design implementation on 40nm, 28nm or 20nm technology
- Should be a power user of P&R and timing analysis CAD tools from Synopsys (ICC/DC/PT/STAR-RC)
- Cadence (First Encounter)
- Place/ route and tapeout solutions
2
Physical Design Engineer Job Description
Job Description Example
Our company is growing rapidly and is hiring for a physical design engineer. Please review the list of responsibilities and qualifications. While this is our ideal list, we will consider candidates that do not necessarily have all of the qualifications, but have sufficient experience and talent.
Responsibilities for physical design engineer
- Place and route at chip level, or block level, including placement, clock tree synthesis, routing, signal integrity for designs with complex clock tree implementations
- Defining and debugging Timing Constraints and performing STA using industry standard STA engines and using a thorough understanding of timing correlation, to achieve timing closure
- Responsible for Front-End chip implementation including design integration, synthesis and execution flows that starts with RTL coding and ends with the delivery of a netlist package ready for physical design
- Responsible for synthesis, netlist generation, timing and logical equivalency checks, floorplanning, budgeting, clock methodology and timing constraint management
- As member of physical/implementation design team, drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists and drive execution
- Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure
- Resolve design and flow issues related to physical design, identify potential solutions
- Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers with the RTL design team
- Back-end engineer for ARM based MPU design(s)
- Co-design Engineer
Qualifications for physical design engineer
- Expertise and in-depth knowledge of industry standard EDA tools required
- Proficiency in scripting languages, such as, Perl, Tcl, Make, required
- EE degree with 5+ years of experience or MSEE with 3+ years of experience, preferably with high speed multi-gigabit SerDes PHY designs or other high performance IP designs
- 7-10 years of hands-on experience in physical design on ASIC tapeouts
- Experienced with ASIC design flow, hierarchical physical design strategies, methodologies
- Understanding of deep sub-micron technology issues
3
Physical Design Engineer Job Description
Job Description Example
Our growing company is searching for experienced candidates for the position of physical design engineer. Please review the list of responsibilities and qualifications. While this is our ideal list, we will consider candidates that do not necessarily have all of the qualifications, but have sufficient experience and talent.
Responsibilities for physical design engineer
- Constraint file generation, Clock Tree Synthesis
- Must have experience in completing PD tasks on recent Technologies (22nm, 14 nm, 7nm, and beyond)
- Work with various engineers and teams to successfully tapeout ASICs on-time and with high quality
- Communicate clearly both verbally and in writing to peers and management
- Work closely with design engineers to interpret schematics and drive physical implementation
- Build and verify all levels of physical design hierarchy using in-house tools
- Collaborate closely with other SoC projects at various sites across
- Will be responsible to lead/implement multiple blocks, may need to mentor or lead a small group of engineers, track their block convergence, effectively communicate with Fullchip or front end teams actively for the smooth closure of blocks
- Build and integrate all levels of physical design hierarchy using in-house tools
- Chip level floor-planning
Qualifications for physical design engineer
- Hands on experience in logic synthesis and equivalence checking/FV required
- The ideal candidate will have 3 plus years of hands on experience in physical design and large chip integration
- The candidate will perform Netlist to GDSII implementation of digital designs at the macro or core level
- The ideal candidate will have hands on experience in physical design and large chip integration
- Two years relative work experiences are preferred
- Professional Engineer (PE) license strongly desired
4
Physical Design Engineer Job Description
Job Description Example
Our growing company is looking for a physical design engineer. If you are looking for an exciting place to work, please take a look at the list of qualifications below.
Responsibilities for physical design engineer
- Co-ordinating between design verification, DFT and implementation activities
- Participate and lead others in developing scripts/methodologies/flows automation and improvements to the backend design flow
- Communication and collaboration with the circuit development team to achieve the optimum matching between transistor level schematics and physical design
- Power supply and power grid planning and analysis
- Debug and resolution of integration issues at parent level
- Completion of design reviews and design signoff flows
- Low power verification using CLP/FV and Physical Verification to run all PV checks such as DR, LVS, ERC based on a deep understanding of all the rules and fixes
- Work in collaboration with Physical Design Engineers in chip level planning and integrations
- Post layout timing analysis
- Test Vector Generation
Qualifications for physical design engineer
- Able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure
- Must be able to take the Hardmacro through P&R from Netlist to GDS including timing closure, formal and Physical verification
- BE plus 8 years, or ME plus 5 years, in deep-sub-micron IC physical designs, or equivalent experience
- Experience with TCL and Perl, to achieve higher productivity, is desired
- Posses a Bachelors of Science degree in EE or CS or a Natural Science
- Advance low power (leakage & dynamic) reduction techniques
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Physical Design Engineer Job Description
Job Description Example
Our company is searching for experienced candidates for the position of physical design engineer. Please review the list of responsibilities and qualifications. While this is our ideal list, we will consider candidates that do not necessarily have all of the qualifications, but have sufficient experience and talent.
Responsibilities for physical design engineer
- Participate in developing scripts/methodologies/flows automation and improvements to the back end design flow
- Working on physical verification group for dGPU projects, includs DRC/LVS
- Co-working with other teammates or external team to solve problems
- Other jobs needed from physical verification field
- Physical design of digital blocks and full chip activities
- Own RTL to GDS delivery
- May also include low power implementation (UPF) based on experience
- Generate and maintain common scripts for physical design flow that team members will use
- Layout high speed analog and mixed-signal custom chips for the hard disk drive industry
- Work directly with a team of engineers to determine floor plan, routing and I/O requirements for preamp IC's
Qualifications for physical design engineer
- Self starter with 2-12 years of experience on SOC/Chip level/IP physical design on multimillion Gate and complex design with multiple clocks and power domains with minimal supervision
- Expertise in clock tree closure from Frequency/Power/EMC/Reliability perspective
- Sound knowledge of electrical physical constraints/rules is desired (Physical integration including floor-planning, padring integration, power grid, Power/IR analysis, reliability)
- Good communication skills strong willingness to learn from more experienced engineers
- The ideal candidate will have at least 5+ years of Physical Design experience on high PHY and/or SOC designs
- Manage deliverables.Communicate clearly both verbally and in writing