Asic Verification Engineer Resume Samples
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Asic Verification Engineer Resume Samples
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LL
L Legros
Lon
Legros
88688 Einar Square
Houston
TX
+1 (555) 233 3121
88688 Einar Square
Houston
TX
Phone
p
+1 (555) 233 3121
Experience
Experience
Los Angeles, CA
Asic Verification Engineer
Los Angeles, CA
MacGyver-Von
Los Angeles, CA
Asic Verification Engineer
- Develop stressful testplan
- Extending existing verification environments to improve the quality of testing
- Working with design engineers to resolve the specification of complex hardware components, and creating verification specifications
- Create testcase to ensure maximum coverage
- Developing and maintaining models for various APU and dGPU IPs
- Develop verification IP which can be reused at different levels of verfication: block level, sub-system level, SoC level, etc
- Working with design and firmware engineers to verify all of the key features
Los Angeles, CA
Lead Asic Verification Engineer
Los Angeles, CA
Champlin and Sons
Los Angeles, CA
Lead Asic Verification Engineer
- Lead, mentor, and Direct more engineers on the team, manage and track verification development schedules
- Develop the actual UVM DV Agent (Monitor, Driver, ScoreBoard)
- Develop/Modify Perl/Bash/Python scripts
- Develop SystemVerilog/UVM testbenches at Top/Sub-system/Block-levels
- Debug, report, and work closely with design engineers
- Develop/Integrate C/C++/Matlab Reference models into the testbench
- Communicate with the team and execute the test plans in timely matter
present
San Francisco, CA
Senior Asic Verification Engineer
San Francisco, CA
Franecki-Marvin
present
San Francisco, CA
Senior Asic Verification Engineer
present
- + Working with architects to understand features to be implemented and verified
- Drive chip level testplan development and execution
- Engage in verification environment architecture and methodology development
- + Create and maintain the block level test bench
- + Debug test failures to determine if it is a design or verification issue; work with the design team to correct defects and test issues
- + Create directed and random block level verification tests
- + You might also be responsible for the creation of C models for a portion of the design
Education
Education
Bachelor’s Degree in Electrical
Bachelor’s Degree in Electrical
North Carolina State University
Bachelor’s Degree in Electrical
Skills
Skills
- Knowledge of networking standards such as SONET (OR) OTN/G.709 and Layer 2/3 networking protocols is desired 8. Networking and packet based protocol experience is desired
- Our employees are the reason we have been successful in the past and the reason we will be successful in the future. Employees’ skills, talents and work ethic have defined the business and will shape our collective future
- Good knowledge in Verilog HDL - an advantage
- Strong communication skills, with the ability to convey complex technical concepts to other peers in verbal and written form
- Knowledge in Ethernet - an advantage
- Knowledge of SystemVerilog/VMM/OVM/UVM verification methodologies; experience with code coverage, functional coverage, formal verification tools
- Strong execution orientation
- Fluent English (both written and spoken) and excellent communication skills
- Demonstrated ability to work independently as well as in a multi-disciplinary group environment
- Extending existing verification environments to improve the quality of testing
15 Asic Verification Engineer resume templates
Read our complete resume writing guides
1
Senior Asic Verification Engineer Resume Examples & Samples
- Proficient in SystemVerilog
- Extensive experience in asic verification using SytemVerilog
- Constrained-random verification a strong plus
- Experience with verification methodology like OVM/VMM/UVM desired
- Perl/Tcl scripting is strongly preferred
- Experience designing asics for networking protocols (Ethernet, FCoE) a plus
- Must be strong at documenting the verification plan and presentations
- Strong problem solving and asic debugging skills
- MSEE with 8+ or BSEE with 10+ years of related experience is required
2
MTS Asic Verification Engineer Resume Examples & Samples
- Development, enhancement, and automation of existing accelerated verification solution
- Implementation of bus functional models to enable verification of new HW features in C++ and Verilog
- Developing detailed verification acceleration plans for all aspects of video IP in collaboration with IP architects, designers and verification engineers
- Working with ASIC design and firmware teams to debug test failures including identifying the root cause, suggesting possible fixes, and working together to implement and resolve issues in a timely manner
- Architecting, implementing, and prototype testing the next generation of FPGA based accelerated verification solution. This includes specification, implementation, test plan, testbench, associated test libraries or APIs, and supporting hardware models/checkers
- Mentoring junior verification team members including students and providing advices on problem solving for underling accelerated verification platform
3
Senior. / MTS Asic Verification Engineer Resume Examples & Samples
- Work with RTL designer to get a full deep insight on the design under test
- Build testbench
- Create testcase to ensure maximum coverage
4
Asic Verification Engineer Resume Examples & Samples
- Working with architects to understand features to be implemented and verified
- Create and maintain the block level test bench
- Review functional and code coverage metrics - modify or add tests to meet coverage requirements
- You might also be responsible for the creation of C models for a portion of the design
5
Senior Asic Verification Engineer Resume Examples & Samples
- Write the block level test plan
- Create directed and random block level verification tests
- Review functional and code coverage metrics – modify or add tests to meet coverage requirements
- Debug test failures to determine if it is a design or verification issue; work with the design team to correct defects and test issues
6
Asic Verification Engineer Resume Examples & Samples
- Writing and reviewing verification specifications
- Design and development of test environments and test benches in multiple languages
- Implementation of test cases in SystemVerilog/UVM
- 0-2 years of professional experience of ASIC verification required
- Experience from other languages such as C/C++, Tcl, Perl is a benefit
- Located in the Copenhagen area or willing to relocate. In possession of an EU work permit
7
Asic Verification Engineer Resume Examples & Samples
- Defining, designing & verifying, modeling, and implementing of controllers for Micron's SSD efforts
- Developing design specifications, conducting hardware architecture & design tradeoffs, mapping NAND management algorithms into hardware implementations, performing logic design, implementation and block verification
- Working in close collaboration as part of a team that includes other Digital Designers, Verification and Firmware Engineers, System and Algorithm Engineers, Physical Design Engineers and FPGA Engineers
- Good knowledge in Verilog/SystemVerilog and verification methodology; knowledge of C or other HVL would be a plus
- Good communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form
- A high level of self-motivation and the ability to be a self-starter
- Good written, verbal and presentation communication skills
- BS in EE/CS MS in EE/CS
8
Senior Asic Verification Engineer Resume Examples & Samples
- Definition and development of test environments and test benches in multiple languages
- Implementation of test cases in SystemVerilog
- Lab validation of ASIC devices
- MSEE or equivalent required
- 3-5 years of professional experience of ASIC verification required
- Experience with VHDL or Verilog and related simulators required
- Experience with SystemVerilog/UVM is a strong benefit
- Experience from development of data communication devices is a benefit
9
Co-op Asic Verification Engineer Resume Examples & Samples
- Develop Verilog test cases for the verification of a mixed signal ASIC for an optical modem
- Provide debug assistance for the ASIC design
- Write scripts to automate some tasks of the ASIC design and verification process
- Create scripts and run validation test in the lab
- Strong programming experience in C, Verilog and/or SystemVerilog
- Solid knowledge of digital circuit design and verification
- Working knowledge of DSP and communication theories
- Experience with Matlab and tcl will be an asset
- Great communication skills and team work
- MS candidate or senior BS student in Electrical or Computer Engineering
10
Asic Verification Engineer Resume Examples & Samples
- Logic design and verification related to the development of SSD controller chips
- Master’s degree in Electrical Engineering with a focus VLSI development
- Verilog and experience with verification tools
11
Asic Verification Engineer Resume Examples & Samples
- Join a verification team responsible for the verification of state of the art networking ASIC designs
- As part of the verification effort, new and advanced re-use methodologies are used
- Full verification flow block-level to sub-chip and full-chip benches, formal verification and many more
- Must have experience in ASIC Verification using one of the following HVLs: Specman , SystemVerilog
- Must have experience with advanced verification methodologies (constraint random, coverage driven, verification reuse) as UVM , eRM, VMM, OVM
- Knowledge in Ethernet - an advantage
- Knowledge in PCIe - an advantage
- Experience with Formal Verification - an advantage
- Good knowledge in Verilog HDL - an advantage
- Experience with scripting - an advantage
- Initiative, Ownership,Open minded
- Strong execution orientation
12
Asic Verification Engineer Resume Examples & Samples
- 5-10 years Analog and digital ASIC design/verification experience
- Through understanding of ASIC design methodologies, flow, and tools
- Hands on experience in cadence verification tools, AMS model development, and functional verification/simulation
- Some experience with a processor assembly language
- Understanding of concepts, ATE methodologies, and ATE vector development is desirable
- Enjoys working in a highly collaborative (global) team environment
13
Asic Verification Engineer Resume Examples & Samples
- Developing and maintaining complex verification environments using various methodologies, including Self-checking, reusable, automated verification environment, Constrained random generators and reference models
- Developing and maintaining models for various APU and dGPU IPs
- Writing and executing testplans for IP and SOC level verification
- Contributing to creation and adoption of new verification methodologies
- Occasional creation of utility software using C++, Perl, php
- Working with design and firmware engineers to verify all of the key features
14
Senior Asic Verification Engineer Resume Examples & Samples
- 7+ Years design verification experience (SystemVerilog or Verilog based)
- Knowledge of SystemVerilog assertions
- Strong leadership and communication skills, with the ability to convey complex technical concepts to other peers in verbal and written form
- A proven ability to achieve results in a fast moving, dynamic environment
15
Principal Asic Verification Engineer Resume Examples & Samples
- BSEE or MSEE/ECE degree with 6+ years of experience in complex IP and SOC test environments
- Hands on experience with SV UVM and an object oriented testbench
- Ability to work in a constrained pseudo-random test environment
- History of creating high quality testplans from design specifications
- Ability to work in a cross-functional environment and be a team player who is inquisitive and self-motivated
16
Lead Asic Verification Engineer Resume Examples & Samples
- Develop the actual UVM DV Agent (Monitor, Driver, ScoreBoard)
- Write comprehensive verification test plans
- Derive, generate, and track the coverage metrics
- Develop SystemVerilog/UVM testbenches at Top/Sub-system/Block-levels
- Debug, report, and work closely with design engineers
- Communicate with the team and execute the test plans in timely matter
- Develop Re-usable UVM Verification IPs or UVM Verification Components (UVC)
- Develop/Integrate C/C++/Matlab Reference models into the testbench
- Develop/Modify Perl/Bash/Python scripts
- Lead, mentor, and Direct more engineers on the team, manage and track verification development schedules
- Bachelor of Science in Electrical Engineering or Computer Science
- 8+ years of experience VMM/OVM/UVM development in verification on unix-based platforms
- Team Leadership & project ownership, the candidate must have lead verification teams of 3 or more in the past
- 8+ years of experience in Code coverage, also constrained random and directed test development and coverage specification and analysis
- Must have verified at least 5 production ASICs
- Masters of Science or PhD in Electrical Engineering or Computer Science
- Expert level knowledge of test bench development using Object Oriented System Verilog
- Building complete UVM based test bench environments from scratch
- Developing Drivers, Monitors, Sequencers, Agents, Scoreboards, Checkers, etc
- Proficient in System Verilog
- Experience with automated regression test development
- Detailed experience in shell programming language such as bash, csh, KSh, sh
- Detailed experience in scripting language such as Perf, Perl, TCL, SED, Python, make file, etc
- ASIC test plan development, definition, and specification
- BFM development for a wide variety of common embedded processors
- Experience with emulation platform (like Mentor Veloce or Cadence Palladium)
- Experienced with porting other language models (like Matlab Models) in verification environment
- Cache Architectures,
- Formal verification using Conformal and/or Formality
- Verification of mixed signal, and wireless communication ASICs
- Lab experience with logic analyzers and oscilloscopes
- Logic Synthesis: Design Compiler, Test Compiler, Prime Time, RC RTL compiler,
- Revision Control Systems: perforce, svn, cvs, git, clearcase
17
Senior Asic Verification Engineer Resume Examples & Samples
- Bachelor of Science Degree in computer engineering or electrical engineering
- 8+ years of experience verifying complex ASICs / FPGAs
- 5+ years of experience in ASIC / FPGA verification using C/C++ and/or System Verilog
- 5+ years of experience with verification methodology like OVM / UVM / MM
- 5+ years of experience with building and setting up scalable simulation / verification environments
- 3+ years of experience with scripting (bash/csh, Perl, TCL, Python, etc.)
- Master’s Degree in Computer Engineering, Electrical Engineering or equivalent
- Constrained Random Verification Experience, highly desired
- Being familiar with System Verilog Assertions
- Sufficient familiarity with scripting languages (bash/csh, Perl, TCL, Python, etc.)
- Exposure to other tools (like synthesis, power analysis, coverage, …)
- Some VHDL experience is desired
- Experience with high reliability design and implementations
- Familiarity with testing complex designs, code coverage, functional coverage, assertions
- Knowledge of Digital signal processing
- Demonstrate the ability to work in a dynamic environment
18
Senior Asic Verification Engineer Resume Examples & Samples
- At least 7+ years of experience in chip design and verification languages such as SystemVerilog or Specman (E)
- Expertise in advanced DV methodologies as UVM or ERM
- Proven experience in leading Verification activities in all levels
- Strong object oriented programming capabilities
- Experience in coverage driven methodologies
- Strong verbal and written communication skills, both in Hebrew and English
- Independent problem solving skills and excellent troubleshooting capabilities
19
Principal Asic Verification Engineer Resume Examples & Samples
- Previously developed packet based test bench using UVM verification methodology
- Experience in creating and maintaining block level test benches and converting them for top level usage
- Experience in random and directed test methods, coverage analysis (code coverage and functional coverage) and score boarding
- Strong System Verilog coding skills
- Understanding of ASIC design and hands on RTL coding skills
- Experience with high speed and network interfaces (e.g. SERDES, GigE, 10GE, etc.)
- Expertise in Ethernet MAC and IP transport
- SOC architectures, high speed interconnect buses such as AHB, APB and interfaces such as SERDES, I2C, MPEG transport, Ethernet
- Knowledge and hands-on experience with Ethernet packets, mpeg transport packets and time synchronization
- Exposure to communications/DSP building blocks and/or SOC functional modules
- Experienced with Ethernet MAC and PHY, physical layer devices/transceivers, switching fabric
- Experienced with layer 2, layer 3 switching and networking protocols, e.g. Ethernet, L2TP tunneling, IP forwarding, MPLS, switching, routing, and packet processing
- Experience with MPEG TS (transport stream) and video delivery using MPEG TS
- Strong logical and creative problem-solving skills with excellent analytical and debugging skills
- Must be a flexible self-starter who can ramp up with new technologies, products, etc
- Motivated, and able to work effectively under pressure
- BS/MS CS/EE degree and 10 years of experience or Ph.D. and 6 years of experience
20
Asic Verification Engineer Resume Examples & Samples
- Educated to degree level in electronics
- 1 year electronics experience is desirable. Graduate Electronic Engineer may also apply
- Experience in electronic design and verification
- Experience in writing up test specifications and reports
- Experience in the use of National Instruments LabVIEW would be advantageous
- Knowledge of digital and analogue electronic circuitry is desirable
- Organised
- Team player and self-motivated
- Comfortable to interface with the internal customers during problem resolution
- Good literacy in MS Office
21
Senior Asic Verification Engineer Resume Examples & Samples
- B.Tech with Experience (8-10 yrs) in Design verification of complex IP blocks
- Experience in multible IP's DV using SV/UVM & good knowledge of a scripting language (perl/python)
- Hands on experience with latest DV tools/Simulators/Methodologies
- M.tech qualification is desirable
- Experience of working at Fullchip/Sub-system level test benches is also desireable
22
Asic Verification Engineer Resume Examples & Samples
- 3+ year working experience of PCIe protocol knowledge
- NVMe protocol knowledge is a plus but not must
- 5+ year Working experience in IP / SoC verification using UVM, OVM or System Verilog
- Expertise in developing block level / system level verification environments
- Expertise to develop BFMs / Checkers / monitors / Scoreboards
- Knowledge of scripting languages like Perl and Unix Shell language
- CAD Tools : Synopsys/Cadence
- MS degree in Electrical Engineering or Computer Engineering
23
Asic Verification Engineer Resume Examples & Samples
- Working with design engineers to resolve the specification of complex hardware components, and creating verification specifications
- Implementation of verification environments using System Verilog/UVM, formal verification, and a range of other verification tools and methodologies
- Defining coverage metrics and ensuring that verification meets those targets
- Extending existing verification environments to improve the quality of testing
24
Senior Asic Verification Engineer Resume Examples & Samples
- Participate in architecture definition and modeling
- Contribute to micro-architecture specification and reviews
- Engage in verification environment architecture and methodology development
- Drive chip level testplan development and execution
- Engage in post-silicon bringup and validation
- Foster cross functional collaboration with design, software and hardware teams to ensure a successful product delivery
- Mentor and enable other engineers
- Experience in high-performance ASIC verification
- Good understanding of ASIC design and verification methodologies and flows
- Hands-on experience with HVL and HDL languages and tools, scripting and programming languages (Verilog, SV, C++, Perl, etc.)
- Good understanding of random stimulus generation methodology
- UVM knowledge a plus
- Good communication skills and a team player
- Networking knowledge preferred, but not essential
25
Asic Verification Engineer Resume Examples & Samples
- 4+ years’ experience in ASIC/FPGA Verification
- Strong Verilog, SystemVerilog, C/C++, and Perl/Python/shell scripts programming skills
- Knowledge of SystemVerilog/VMM/OVM/UVM verification methodologies; experience with code coverage, functional coverage, formal verification tools
- Participation in a recent multi-million gate ASICs verification in telecom/networking area is preferred
- Should have worked on developing test plans at module/chip-level for the project
- Knowledge of networking standards such as SONET (OR) OTN/G.709 and Layer 2/3 networking protocols is desired 8. Networking and packet based protocol experience is desired
