Awnind Abhay Shrivastava
Design Verification Engineer
Hyderabad,IN
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Summary
- Proficient in Verilog , System Verilog and setting up class based environment using System Verilog/UVM.
- Experience in developing sub system level test cases using UVM.
- Experience in Infrastructure work including maintaining and fixing scripts to do legal checks.
- Strong programming skills using Python/Perl.
Experience
2018
Dec
-
Present
Engineer 1
Soctronics Technologies Pvt. Ltd. / Hyderabad
- Execute verification test plan by developing sub system level test cases using SystemVerilog/UVM.
- Analyse results and follow up with design team to update revisions to meet design intent.
- Develop and maintain scripts to verify memory dump from multiple ports using Python.
- Develop and troubleshoot scripts used in log checking and compilation using Perl/Python.
- Implement UVM monitor for top/sub-system level testbench , enable transaction tracker file for easy debug.
- Provide support in SoC deployment , develop and maintain scripts for obfuscation and removal of confidential keywords.
- Work closely with infrastructure team on customer delivery flow to share the design source and test cases with client.
2018
Jan
-
2018
Dec
Logic Design Intern
VEDA Institute of Information Technolgy / Hyderabad
- Advance Diploma in Digital Logic Design and Verification sponsored by Soctronics Technologies Pvt. Ltd.
Education
2013
-
2017
Dr. A.P.J Abdul Kalam Technical University
Bachelor of Technology in Electronics and Communication
Skills
